Micro-Threaded Memory
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Accused Products
Abstract
A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.
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Citations
24 Claims
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1. (canceled)
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2. A synchronous memory device, comprising:
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first and second bank groups, each comprising at least two storage arrays; and a request interface to receive external commands corresponding to memory transactions, including row activate commands and column access commands, each addressed to one of the storage arrays, the request interface having row control circuitry to service two row activate commands addressed to respective storage arrays in different ones of the bank groups with a shorter intervening interval than the row control circuitry can service two row activate commands addressed to respective storage arrays in a same one of the bank groups, the request interface having column control circuitry to service two column access commands directed to respective, active rows in respective storage arrays in different ones of the bank groups with a shorter intervening interval than the column control circuitry can service two column access commands directed to one or more active rows in a same one of the bank groups. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A synchronous memory device, comprising:
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first and second bank groups, each comprising at least two storage arrays; a request interface to receive external commands corresponding to memory transactions, including row activate commands and column access commands, each addressed to one of the storage arrays; circuitry coupled to the request interface and responsive to the external commands to cause the retrieval of read data associated with each memory read transaction from memory cells of at least one of the storage arrays; and a data interface to externally exchange the read data; wherein the memory device is characterized by a first timing requirement from a first row activate command directed to a storage array in the first bank group to another row activate command directed to another storage array in the first bank group, and a second timing requirement from the first row activate command to another row activate command directed to a storage array in the second bank group, the second timing requirement being shorter than the first timing requirement; and wherein the memory device is further characterized by a third timing requirement from a first column access command directed to a first open row in a storage array in the first bank group to another column access command directed to an open row associated with the first bank group, and a fourth timing requirement from the first column access command to another column access command directed to an open row associated with the second bank group, the fourth timing requirement being shorter than the third timing requirement. - View Dependent Claims (18, 19, 20, 21, 22)
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23. A synchronous memory device, comprising:
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first and second bank groups, each comprising at least two storage arrays; a request interface to receive external commands corresponding to memory transactions, including row activate commands and column access commands, each addressed to one of the storage arrays; row control circuitry coupled to the request interface to open a row in at least one addressed storage array responsive to each row activate command; column control circuitry coupled to the request interface to cause retrieval of column-specified read data from an open row in at least one addressed storage array responsive to each column access command; a data interface to externally exchange the column-specified read data; wherein the row control circuitry is characterized by a first timing requirement from a first row activate command to open a first row in a storage array in the first bank group to another row activate command to open another row in another storage array in the first bank group, and a second timing requirement from the first row activate command to another row activate command to open another row associated with the second bank group, the second timing requirement being shorter than the first timing requirement; and wherein the column control circuitry is characterized by a third timing requirement from a first column access command directed to the first open row to another column access command directed to an open row in the first bank group, and a fourth timing requirement from the first column access command to another column access command directed to an open row in the second bank group, the fourth timing requirement being shorter than the third timing requirement. - View Dependent Claims (24)
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Specification