Dual Mode Write Non-Volatile Memory System

• US 20130268726A1
• Filed: 12/30/2011
• Published: 10/10/2013
• Est. Priority Date: 07/01/2011
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Guo, Xin, Pangal, Kiran, Ruby, Paul D., Zhu, Feng
• Application Number:
  US13/993,596
• Publication Number:
  US 20130268726A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Host writes may be handled differently from background writes to non-volatile memory systems. As a result of using different write algorithms for host writes and backgrounds writes, maximum system lifetime and the maximum system performance may be improved in some embodiments.

Claims

1. A method comprising:

identifying an originator of a write request to non-volatile memory dice; and

writing to the dice differently depending on the originator of the write request.

2. The method of claim 1 including distinguishing host originated writes from other write requests.

3. The method of claim 2 including receiving write requests in a flash memory system.

4. The method of claim 3 including handling writes from outside the flash memory system differently than writes originating within the system.

5. The method of claim 4 including implementing host originated writes differently than background writes.

6. The method of claim 2 including establishing a default mode to implement at least one of host or background writes and when the write request is identified as being other than the default mode, changing the mode to implement the write and then reverting to the default mode after completing the write.

7. The method of claim 6 including changing the mode by changing the trim profile.

8. The method of claim 7 including providing user selectable trim profiles.

9. The method of claim 1 including selecting one of single level or multi-level modes for the default write mode.

10. The method of claim 9 including using one of touch-up programming or corrective programming for background writes.

11. The method of claim 10 including rewriting host written data with the background write algorithm.

12. A non-transitory computer readable storage medium storing instructions to enable a controller to:

identify an originator of a write request to non-volatile memory dice; and

write to the dice differently depending on the originator of the write request.

13. The medium of claim 12 further storing instructions to distinguish host originated writes from other write requests.

14. The medium of claim 13 further storing instructions to handle writes from outside a flash memory system differently than writes originating within the system.

15. The medium of claim 14 further storing instructions to implement host originated writes differently than background writes.

16. The medium of claim 13 further storing instructions to establish a default mode to implement at least one of host or background writes and when the write request is identified as being other than the default mode, change the mode to implement the write and then reverting to the default mode after completing the write.

17. The medium of claim 16 further storing instructions to change the mode by changing the trim profile.

18. The method of claim 17 further storing instructions to provide user selectable trim profiles.

19. The method of claim 12 further storing instructions to select one of single level or multi-level modes for the default write mode.

20. The method of claim 19 further storing instructions to use one of touch-up programming or corrective programming for background writes.

21. An apparatus comprising:

a controller; and

firmware in said controller to identify an originator of a write request to non-volatile memory dice and write to the dice differently depending on the originator of the write request.

22. The apparatus of claim 21 said firmware to distinguish host originated writes from other write requests.

23. The apparatus of claim 22 wherein said controller is a flash memory controller.

24. The apparatus of claim 23 said firmware to handle writes from outside the flash memory controller differently than writes originating within the controller.

25. The apparatus of claim 24 said firmware to implement host originated writes differently than background writes.

26. The apparatus of claim 22 said firmware to establish a default mode to implement at least one of host or background writes and when the write request is identified as being other than the default mode, change the mode to implement the write and then reverting to the default mode after completing the write.

27. The apparatus of claim 26 said firmware to change the mode by changing the trim profile.

28. A system comprises:

a processor;

a solid state drive, coupled to said processor including a controller;

firmware in said controller to identify an originator of a write request to non-volatile memory dice and write to the dice differently depending on the originator of the write request; and

a network interface card coupled to said processor.

29. The system of claim 28, said firmware to select one of single level or multi-level modes for as a default write mode.

30. The system of claim 29, said firmware to use one of touch-up programming or corrective programming for background writes.