SEMICONDUCTOR DEVICE

• US 20130270552A1
• Filed: 04/11/2013
• Published: 10/17/2013
• Est. Priority Date: 04/13/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, MATSUBAYASHI, Daisuke, MURAYAMA, Keisuke
• Granted Patent: US 8,946,702 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.

Claims

1. A semiconductor device comprising:

a first gate electrode layer over an insulating surface;

a first insulating layer over the first gate electrode layer;

oxide semiconductor stacked layers comprising a first oxide semiconductor layer and a second oxide semiconductor layer and overlapping with the first gate electrode layer with the first insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers;

a source electrode layer and a drain electrode layer over and in contact with the second oxide semiconductor layer;

a second insulating layer over and in contact with the source electrode layer, the drain electrode layer, and part of the oxide semiconductor stacked layers; and

a second gate electrode layer overlapping with the oxide semiconductor stacked layers with the second insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers,

wherein a region in contact with the second insulating layer in the oxide semiconductor stacked layers has a smaller thickness than a region in contact with the source electrode layer and a region in contact with the drain electrode layer in the oxide semiconductor stacked layers.

2. The semiconductor device according to claim 1,

wherein the first oxide semiconductor layer comprises indium and gallium, and

wherein an indium content is higher than a gallium content in the first oxide semiconductor layer.

3. The semiconductor device according to claim 1,

wherein the second oxide semiconductor layer comprises indium and gallium, and

wherein an indium content is lower than or equal to a gallium content in the second oxide semiconductor layer.

4. The semiconductor device according to claim 1, wherein at least one of the first gate electrode layer and the second gate electrode layer is a conductive layer having a work function of 5 eV or more.

5. The semiconductor device according to claim 1, wherein at least one of the first gate electrode layer and the second gate electrode layer is an In—

Ga—

Zn—

O film comprising nitrogen.

6. A semiconductor device comprising:

a first gate electrode layer over an insulating surface;

a first insulating layer over the first gate electrode layer;

oxide semiconductor stacked layers comprising a first oxide semiconductor layer and a second oxide semiconductor layer and overlapping with the first gate electrode layer with the first insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers;

a source electrode layer and a drain electrode layer over and in contact with the second oxide semiconductor layer;

a second insulating layer over and in contact with the source electrode layer, the drain electrode layer, and part of the oxide semiconductor stacked layers; and

a second gate electrode layer overlapping with the oxide semiconductor stacked layers with the second insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers,

wherein the first oxide semiconductor layer and the second oxide semiconductor layer have same constituent elements and different compositions of the constituent elements; and

wherein a region in contact with the second insulating layer in the oxide semiconductor stacked layers has a smaller thickness than a region in contact with the source electrode layer and a region in contact with the drain electrode layer in the oxide semiconductor stacked layers.

7. The semiconductor device according to claim 6,

wherein the first oxide semiconductor layer comprises indium and gallium, and

wherein an indium content is higher than a gallium content in the first oxide semiconductor layer.

8. The semiconductor device according to claim 6,

wherein the second oxide semiconductor layer comprises indium and gallium, and

wherein an indium content is lower than or equal to a gallium content in the second oxide semiconductor layer.

9. The semiconductor device according to claim 6, wherein at least one of the first gate electrode layer and the second gate electrode layer is a conductive layer having a work function of 5 eV or more.

10. The semiconductor device according to claim 6, wherein at least one of the first gate electrode layer and the second gate electrode layer is an In—

Ga—

Zn—

O film comprising nitrogen.