INTEGRATED CIRCUIT SELF ALIGNED 3D MEMORY ARRAY AND MANUFACTURING METHOD

• US 20130270626A1
• Filed: 06/07/2013
• Published: 10/17/2013
• Est. Priority Date: 03/03/2009
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lue, Hang-Ting
• Granted Patent: US 8,780,602 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers.

Claims

1. A memory device, comprising:

a substrate;

a stack of conductive strips, including a first one of the conductive strips with a first current path, and a second one of the conductive strips with a second current path;

a first gate structure and a second gate structure over the stack of conductive strips at different positions along the stack of conductive strips, the first gate structure and the second gate structure substantially perpendicular to the substrate;

a first memory element between the first current path and the first gate structure; and

a second memory element between the first current path and the second gate structure.

2. The memory device of claim 1, wherein neighboring conductive strips in the stack of conductive strips are separated by insulating material.

3. The memory device of claim 1, comprising:

a word line having a surface that runs along a height of the stack of conductive strips.

4. The memory device of claim 1, comprising:

a plurality of memory elements at a multi-layer array of cross-points between the stack of conductive strips and surfaces of a plurality of conductive lines, the plurality of memory elements establishing a 3D array of memory cells

5. The memory device of claim 1, comprising:

decoding circuits coupled to the stack of conductive strips and to a plurality of word lines, the decoding circuits accessing the first memory element and the second memory element.

6. The memory device of claim 1, wherein the first memory element and the second memory element each comprises an anti-fuse.

7. The memory device claim 1, wherein the first memory element and the second memory element each comprises a charge storage structure.

8. The memory device of claim 1, wherein the first memory element and the second memory element comprise portions of a common layer of memory material between (i) the first gate structure and the second gate structure and (ii) the stack of conductive strips.

9. The memory device of claim 1, including a tunneling layer, a charge trapping nitride layer and a blocking layer between (i) the first gate structure and the second gate structure and (ii) the stack of conductive strips, and wherein said tunneling layer, charge trapping layer and blocking layer in combination form the first memory element and the second memory element.

10. The memory device of claim 1, wherein conductive strips in the stack of conductive strips are formed of n-type semiconductor material.

11. A memory device, comprising:

a substrate;

a plurality of stacked bit lines over the substrate;

a word line over the plurality of stacked bit lines, the word line including a conductive horizontal strip and a conductive vertical extension coupled to the conductive horizontal strip;

a first memory cell disposed between one bit line of the plurality of stacked bit lines and the word line; and

a second memory cell disposed between another bit line of the plurality of stacked bit lines and the word line, wherein the first memory cell and the second memory cell are at different levels from the substrate.

12. The memory device of claim 11, wherein the plurality of stacked bit lines include multiple conductive bit line strips separated by insulating material.

13. The memory device of claim 11, wherein the word line has a surface that runs along a height of the plurality of stacked bit lines.

14. The memory device of claim 11, comprising:

a plurality of memory elements at a multi-layer array of cross-points between the plurality of stacked bit lines and surfaces of the word line, the plurality of memory elements establishing a 3D array of memory cells.

15. The memory device of claim 11, comprising:

decoding circuits coupled to the plurality of stacked bit lines and to the word line, the decoding circuits accessing the first memory cell and the second memory cell.

16. The memory device of claim 11, wherein the first memory cell and the second memory cell each comprises an anti-fuse.

17. The memory device claim 11, wherein the first memory element and the second memory element each comprises a charge storage structure.

18. The memory device of claim 11, wherein the first memory cell and the second memory cell comprise portions of a common layer of memory material between the word line and the plurality of stacked bit lines.

19. The memory device of claim 11, including a tunneling layer, a charge trapping nitride layer and a blocking layer between the word line and the plurality of stacked bit lines, and wherein said tunneling layer, charge trapping layer and blocking layer in combination form a first memory element of the first memory cell and a second memory element of the second memory cell.

20. The memory device of claim 11, wherein bit lines in the plurality of stacked bit lines are formed of n-type semiconductor material.