METHODS OF FORMING FINFET SEMICONDUCTOR DEVICES SO AS TO TUNE THE THRESHOLD VOLTAGE OF SUCH DEVICES

• US 20130270641A1
• Filed: 04/12/2012
• Published: 10/17/2013
• Est. Priority Date: 04/12/2012
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Chi, Min-Hwa
• Granted Patent: US 9,012,286 B2
• Time in Patent Office: Days
• US Class Current: 257/351
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin

Abstract

Disclosed herein are various methods of forming FinFET semiconductor devices so as to tune the threshold voltage of such devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate to define at least one fin (or fins) for the device, prior to forming a gate structure above the fin (or fins), performing a first epitaxial growth process to grow a first semiconductor material on exposed portions of the fin (or fins) and forming the gate structure above the first semiconductor material on the fin (or fins).

Claims

1. A method of forming a FinFET device, comprising:

forming a plurality of spaced-apart trenches in a semiconducting substrate, said trenches defining at least one fin comprised of said semiconducting substrate for said device;

forming a layer of insulating material in said trenches, wherein an exposed portion of said fin extends above an upper surface of said layer of insulating material;

prior to forming a gate structure above said at least one fin, performing a first epitaxial growth process to grow a first semiconductor material on at least a portion of said exposed portion of said at least one fin; and

forming said gate structure above said first semiconductor material on said at least one fin.

2. The method of claim 1, further comprising, after forming said first semiconductor material, but prior to forming said gate structure, performing a second epitaxial growth process to form a second semiconductor material on said first semiconductor material.

3. The method of claim 1, wherein said FinFET device is an N-type FinFET device and wherein said first semiconductor material is comprised of silicon-carbon.

4. The method of claim 1, wherein said FinFET device is a P-type FinFET device and wherein said first semiconductor material is comprised of silicon-germanium.

5. The method of claim 2, wherein said FinFET device is a P-type FinFET device and wherein said first semiconductor material is comprised of silicon-germanium and said second semiconductor material is comprised of silicon.

6. The method of claim 1, wherein said semiconducting substrate is comprised of silicon.

7. The method of claim 1, wherein said first semiconductor material is comprised of silicon, silicon-carbon, silicon-germanium, a III-V compound or a II-VI compound.

8. The method of claim 2, wherein said second semiconductor material is comprised of silicon, silicon-carbon, silicon-germanium, a III-V compound or a II-VI compound.

9. The method of claim 1, wherein said first semiconductor material extends along an entire axial length of said at least one fin.

10. The method of claim 2, wherein said second semiconductor material extends along an entire axial length of said at least one fin.

11. The method of claim 1, wherein said device comprises a plurality of fins and wherein said first semiconductor material is formed on all of the fins in said device.

12. The method of claim 11, wherein, after forming said first semiconductor material on all of the fins in said device, but prior to forming said gate structure, performing a second epitaxial growth process to form a second semiconductor material on said first semiconductor material on all of said fins.

13. The method of claim 1, wherein said first semiconductor material is formed at least at a location on said at least one fin where at least a portion of said gate structure will be formed thereabove.

14. The method of claim 2, wherein said second semiconductor material is formed at least at a location on said at least one fin where at least a portion of said gate structure will be formed thereabove.

15. The method of claim 1, wherein forming said layer of insulating material comprises:

performing a deposition process to form said layer of insulating material to a thickness such that it overfills said trenches; and

performing an etching process to reduce said thickness of said layer of insulating material such that an upper surface of said layer of insulating material is positioned at a level that is below a level of an upper surface of said at least one fin.

16. A method of forming a FinFET device, comprising:

forming a plurality of spaced-apart trenches in a semiconducting substrate, said trenches defining a plurality of fins comprised of said semiconducting substrate for said device;

forming a layer of insulating material in said trenches, wherein an exposed portion of each of said plurality of fins extends above an upper surface of said layer of insulating material;

prior to forming a gate structure above said plurality of fins, performing a first epitaxial growth process to grow a first semiconductor material on at least a portion of said exposed portion of each of said plurality of fins, wherein said first semiconductor material is formed at least at a location on each of said plurality of fins where at least a portion of said gate structure will be formed thereabove; and

forming said gate structure above said first semiconductor material.

17. The method of claim 16, wherein said first semiconductor material extends along an entire axial length of each of said plurality of fins.

18. A method of forming a FinFET device, comprising:

forming a plurality of spaced-apart trenches in a semiconducting substrate, said trenches defining a plurality of fins comprised of said semiconducting substrate for said device;

forming a layer of insulating material in said trenches, wherein an exposed portion of each of said plurality of fins extends above an upper surface of said layer of insulating material;

prior to forming a gate structure above said plurality of fins;

performing a first epitaxial growth process to grow a first semiconductor material on at least portions of said exposed portion of each of said plurality of fins, wherein said first semiconductor material is formed at least at a location on each of said plurality of fins where at least a portion of said gate structure will be formed thereabove; and

performing a second epitaxial growth process to grow a second semiconductor material on at least said first semiconductor material on each of said plurality of fins; and

forming said gate structure above said first and second semiconductor materials.

19. The method of claim 18, wherein said first semiconductor material extends along an entire axial length of each of said plurality of fins.

20. The method of claim 19, wherein said second semiconductor material extends along an entire axial length of each of said plurality of fins

21. A method of forming a FinFET device, comprising:

forming a plurality of spaced-apart trenches in a semiconducting substrate, said trenches defining a plurality of fins comprised of said semiconducting substrate for said device;

forming a layer of insulating material in said trenches, wherein an exposed portion of said fins extends above an upper surface of said layer of insulating material;

forming a hard mask layer that covers said exposed portion of at least one of said plurality of fins but leaves at least one other of said plurality of fins exposed for further processing; and

performing a first epitaxial growth process through said hard mask layer to grow a first semiconductor material on said at least one other of said plurality of fins exposed for further processing.

22. The method of claim 21, further comprising performing a second epitaxial growth process through said hard mask layer to form a second semiconductor material on said first semiconductor material.

23. The method of claim 21, wherein said first semiconductor material extends along an entire axial length of said at least one other of said plurality of fins.

24. The method of claim 22, wherein said second semiconductor material extends along an entire axial length of said at least one other of said plurality of fins.

25. The method of claim 21, wherein forming said hard mask layer comprises:

performing an oxidation process to selectively form an oxidized mask material on said exposed portion of each of said plurality of fins;

after performing said oxidation process, forming a patterned etch mask layer above said plurality of fins that covers said at least one of said plurality of fins but leaves at least one other of said plurality of fins exposed for further processing; and

performing an etching process through said patterned etch mask to selectively remove said oxidized mask material from said at least one other of said plurality of fins.

26. The method of claim 21, wherein forming said hard mask layer comprises:

performing a deposition process to deposit a mask material on said exposed portion of each of said plurality of fins;

after performing said deposition process, forming a patterned etch mask layer above said plurality of fins that covers said at least one of said plurality of fins but leaves at least one other of said plurality of fins exposed for further processing; and

performing an etching process through said patterned etch mask to selectively remove said deposited mask material from said at least one other of said plurality of fins.

27. A FinFET device, comprising:

a fin comprised of a semiconducting substrate;

a first semiconductor layer positioned on at least sidewalls of said fin;

a gate insulation layer positioned above said first semiconductor layer; and

a gate electrode positioned above said gate insulation layer.

28. The device of claim 27, further comprising a second semiconductor layer positioned above said first semiconductor layer, wherein said gate insulation layer is positioned above both of said first and second semiconductor layers.

29. The device of claim 27, wherein said FinFET device is an N-type FinFET device and wherein said first semiconductor layer is comprised of silicon-carbon.

30. The device of claim 27, wherein said FinFET device is a P-type FinFET device and wherein said first semiconductor layer is comprised of silicon-germanium.

31. The device of claim 28, wherein said FinFET device is a P-type FinFET device and wherein said first semiconductor layer is comprised of silicon-germanium and said second semiconductor layer is comprised of silicon.

32. The device of claim 27, wherein said semiconducting substrate is comprised of silicon.

33. The device of claim 27, wherein said first semiconductor layer is comprised of silicon, silicon-carbon, silicon-germanium, a III-V compound or a II-VI compound.

34. The device of claim 27, wherein said second semiconductor layer is comprised of silicon, silicon-carbon, silicon-germanium, a III-V compound or a II-VI compound.

35. The device of claim 27, wherein said first semiconductor layer extends along an entire axial length of said fin.

36. The device of claim 28, wherein said second semiconductor layer extends along an entire axial length of said fin.

37. The device of claim 28 wherein said first and second semiconductor layers are comprised of the same semiconductor material.

38. A FinFET device, comprising:

a first fin and a second fin, each of which are comprised of a semiconducting substrate, said first fin having a bare semiconducting substrate surface;

a first semiconductor layer positioned on at least sidewalls of said second fin;

a gate insulation layer positioned above said bare semiconducting substrate surface of said first fin and said first semiconductor layer on said second fin; and

a gate electrode positioned above said gate insulation layer.

39. The device of claim 38, further comprising a second semiconductor layer positioned above said first semiconductor layer, wherein said gate insulation layer is positioned above both of said first and second semiconductor layers.

40. The device of claim 38, wherein said first semiconductor layer extends along an entire axial length of said second fin.

41. The device of claim 39, wherein said second semiconductor layer extends along an entire axial length of said fin.

42. The device of claim 39 wherein said first and second semiconductor layers are comprised of the same semiconductor material.

47. The device of claim 38 wherein said first and second semiconductor layers are comprised of the same semiconductor material.

43. A FinFET device, comprising:

a first fin and a second fin, each of which are comprised of a semiconducting substrate,

a first semiconductor layer positioned on at least sidewalls of said first and second fins;

a second semiconductor layer positioned above said first semiconductor layer on said second fin;

a gate insulation layer positioned above said first semiconductor layer of said first fin and above said first semiconductor layer and said second semiconductor layer of said second fin; and

a gate electrode positioned above said gate insulation layer.

44. The device of claim 43, further comprising a second semiconductor layer positioned above said first semiconductor layer, wherein said gate insulation layer is positioned above both of said first and second semiconductor layers.

45. The device of claim 43, wherein said first semiconductor layer extends along an entire axial length of said first and second fins.

46. The device of claim 43, wherein said second semiconductor layer extends along an entire axial length of said second fin.