ON-CHIP CAPACITORS AND METHODS OF ASSEMBLING SAME

• US 20130270675A1
• Filed: 10/01/2011
• Published: 10/17/2013
• Est. Priority Date: 10/01/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Fischer, Kevin J., Childs, Michael A., Natarajan, Sanjay S.
• Granted Patent: US 9,627,312 B2
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05016 in side view
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

An on-chip capacitor a semiconductive substrate is fabricated in a passivation layer that is above the back-end metallization. At least three electrodes are configured in the on-chip capacitor and power and ground vias couple at least two of the at least three electrodes. The first via has a first-coupled configuration to at least one of the first- second- and third electrodes and the second via has a second-coupled configuration to at least one of the first- second- and third electrodes.

Claims

1. An on-chip capacitor, comprising:

a semiconductive substrate including an active surface and a backside surface;

a back-end metallization disposed upon the active surface;

a passivation structure disposed upon the back-end metallization, wherein the passivation structure includes;

at least first- second- and third electrodes that are parallel planar;

a first via having a first-coupled configuration to at least one of the first- second- and third electrodes; and

a second via having a second-coupled configuration to at least one of the first- second- and third electrodes, wherein the first coupled configuration is different from the second-coupled configuration.

2. The on-chip capacitor of claim 1, wherein the first and third electrodes are contacted by the first via, and wherein the second electrode is contacted by the second via.

4. The on-chip capacitor of claim 1, wherein the first electrode is contacted by the first via, wherein the second electrode is contacted by the second via, and wherein the third electrode is a floater.

6. The on-chip capacitor of claim 1, wherein the first electrode is contacted by the first via, wherein the second electrode is contacted by the second via, further including the third electrode is contacted by a subsequent via.

7. The on-chip capacitor of claim 1, wherein the first electrode is contacted by the first via, wherein a first subsequent electrode is coplanar with the first electrode and is contacted by the second via, wherein the second electrode is a floater, wherein the third electrode is contacted by the first via, and wherein a third subsequent electrode is coplanar with the third electrode and contacted by the second via.

8. The on-chip capacitor of claim 1, wherein the first and third electrodes are contacted by the first via, wherein the second electrode is contacted by the second via, the on-chip capacitor further including a subsequent electrode disposed above the third electrode and spaced apart by a capacitor dielectric subsequent layer, wherein the subsequent electrode is contacted by the second via, and wherein the second and subsequent electrodes are spaced apart by the third electrode.

9. The on-chip capacitor of claim 1, wherein the first electrode is contacted by the first via, wherein the second electrode is a floater, wherein the third electrode is a floater, and further including a subsequent electrode disposed above the third electrode, wherein the subsequent electrode is contacted by the second via, and wherein the second and subsequent electrodes are spaced apart by the third electrode.

3. (canceled)

5. (canceled)

10. An on-chip capacitor, comprising:

a first via interlayer dielectric layer (VILD) disposed above an upper metallization of a back-end (BE) metallization that is fabricated on a semiconductive substrate;

a patterned first electrode disposed upon the first VILD;

a capacitor first dielectric layer conformally disposed over the patterned first electrode;

a patterned second electrode conformally disposed over the capacitor first dielectric layer;

a capacitor second dielectric layer conformally disposed over the patterned second electrode;

a patterned third electrode conformally disposed over the capacitor second dielectric layer;

a second VILD disposed over the capacitor second dielectric layer and the patterned third electrode;

a first via having a first-coupled configuration to at least one of the first- second- and third electrodes; and

a second via having a second-coupled configuration to at least one of the first- second- and third electrodes, wherein the first coupled configuration is different from the second-coupled configuration.

12. The on-chip capacitor of claim 10, wherein the capacitor dielectric first layer and the capacitor dielectric second layer have the same qualitative chemistries.

13. The on-chip capacitor of claim 10, wherein the capacitor dielectric first layer and the capacitor dielectric second layer have the same qualitative chemistries and different stoichiometries.

15. The on-chip capacitor of claim 10, wherein each electrode that is in contact with a via has a first thickness and each electrode that is a floater has a second thickness that is greater than the first thickness.

16. The on-chip capacitor of claim 10, wherein each electrode that is in contact with a via has a first thickness and each electrode that is a floater has a second thickness that is less than the first thickness.

17. The on-chip capacitor of claim 10, wherein the first and third electrodes are contacted by the first via, and wherein the second electrode is contacted by the second via.

21. The on-chip capacitor of claim 10, wherein the first electrode is contacted by the second terminal, wherein the second electrode is a floater, and wherein the third electrode is contacted by the first via.

25. The on-chip capacitor of claim 10, wherein the first electrode is contacted by the first via, wherein the second electrode is contacted by the second via, and wherein the third electrode is a floater.

31. The on-chip capacitor of claim 10, wherein the first electrode is a floater, wherein the second electrode is contacted by the second via, and wherein the third electrode is contacted by the first via.

38. The on-chip capacitor of claim 10, wherein the first electrode is contacted by the first via, wherein the second electrode is contacted by the second via, further including the third electrode is contacted by a subsequent via.

42. The on-chip capacitor of claim 10, wherein the first electrode is contacted by the first via, wherein a first subsequent electrode is coplanar with the first electrode and is contacted by the second via, wherein the second electrode is a floater, wherein the third electrode is contacted by the first via, and wherein a third subsequent electrode is coplanar with the third electrode and contacted by the second via.

48. The on-chip capacitor of claim 10, wherein the first and third electrodes are contacted by the first via, wherein the second electrode is contacted by the second via, the on-chip capacitor further including a subsequent electrode disposed above the third electrode and spaced apart by a capacitor dielectric subsequent layer, wherein the subsequent electrode is contacted by the second via, and wherein the second and subsequent electrodes are spaced apart by the third electrode.

52. The on-chip capacitor of claim 10, wherein the first electrode is contacted by the first via, wherein the second electrode is a floater, wherein the third electrode is a floater, and further including a subsequent electrode disposed above the third electrode, wherein the subsequent electrode is contacted by the second via, and wherein the second and subsequent electrodes are spaced apart by the third electrode.

80. The on-chip capacitor of claim 10, wherein the substrate is part of a device selected from the group consisting of mobile device, a smartphone device, a tablet computer device, a vehicle, and a television.

11. (canceled)

14. (canceled)

18-20. -20. (canceled)

22-24. -24. (canceled)

26-30. -30. (canceled)

32-37. -37. (canceled)

39-41. -41. (canceled)

43-47. -47. (canceled)

49-51. -51. (canceled)

53-79. -79. (canceled)