METHOD AND APPARATUS FOR LOCAL OSCILLATOR

• US 20130271229A1
• Filed: 04/11/2013
• Published: 10/17/2013
• Est. Priority Date: 04/12/2012
• Status: Abandoned Application

• Current Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Lin, Chi-Hung, Lin, Li, GAO, Xiang
• Application Number:
  US13/861,125
• Publication Number:
  US 20130271229A1
• Time in Patent Office: Days
• US Class Current: 331/19
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

Aspects of the disclosure provide a local oscillator (LO) circuit that includes a first phase locked loop (PLL) circuit and a second PLL. The first PLL circuit is configured to generate a first oscillation signal having a first frequency based on a reference signal having a reference frequency. The second PLL circuit is configured to receive the first oscillation signal and generate a second oscillation signal having a second frequency based on the first oscillation signal.

Claims

1. A local oscillator (LO) circuit, comprising:

a first phase locked loop (PLL) circuit configured to generate a first oscillation signal having a first frequency based on a reference signal having a reference frequency; and

a second PLL circuit configured to receive the first oscillation signal and generate a second oscillation signal having a second frequency based on the first oscillation signal.

2. The LO circuit of claim 1, wherein a periodic signal used in a power amplifier is generated based on the second oscillation signal, and a frequency difference between the first oscillation signal and the periodic signal is larger than a threshold.

3. The LO circuit of claim 2, wherein the first PLL circuit is configured to have a first bandwidth that is smaller than a modulation frequency in the power amplifier and the second PLL circuit is configured to have a second bandwidth that is larger than the modulation frequency in the power amplifier.

4. The LO circuit of claim 1, wherein the first PLL circuit comprises:

a divider configured to frequency-divide the first oscillation signal to generate a feedback signal;

an error detecting and controlling circuit configured to detect an error between the feedback signal and the reference signal and generate a control voltage based on the error; and

a voltage controlled oscillator configured to adjust the first frequency based on the control voltage.

5. The LO circuit of claim 4, wherein the divider is a first divider, the feedback signal is a first feedback signal, the error detecting and controlling circuit is a first error detecting and controlling circuit, the error is a first error, the control voltage is a first control voltage, the voltage controlled oscillator is a first voltage controlled oscillator, and the second PLL circuit comprises:

a second divider configured to frequency-divide the first oscillation signal;

a third divider configured to frequency-divide the second oscillation signal to generate a second feedback signal;

a second error detecting and controlling circuit configured to detect a second error between the second feedback signal and the frequency-divided first oscillation signal and generate a second control voltage based on the second error; and

a second voltage controlled oscillator configured to adjust the second frequency based on the second control voltage.

6. The LO circuit of claim 5, further comprising:

a fourth divider configured to frequency-divide the second oscillation signal.

7. The LO circuit of claim 5, further comprising:

a controller configured to control at least one of the first divider, the second divider and the third divider to adjust the second frequency.

8. The LO circuit of claim 1, wherein the reference signal is a reference oscillation signal.

9. A method, comprising:

receiving a reference signal having a reference frequency;

generating, by a first phase-locked loop (PLL) circuit, a first oscillation signal having a first frequency with phase locked to the reference signal; and

generating, by a second PLL circuit, a second oscillation signal having a second frequency with phase locked to the first oscillation signal.

10. The method of claim 9, further comprising:

generating a periodic signal for use in a power amplifier based on the second oscillation signal, a frequency difference between the first oscillation signal and the periodic signal being larger than a threshold.

11. The method of claim 10, wherein generating the first oscillation signal by the first PLL circuit having a first band width that is smaller than a modulation frequency in the power amplifier;

generating the second oscillation signal by the second PLL circuit having a second bandwidth that is larger than the modulation frequency in the power amplifier.

12. The method of claim 9, wherein generating, by the first PLL circuit, the first oscillation signal having the first frequency with phase locked to the reference signal comprises:

frequency-dividing the first oscillation signal to generate a feedback signal;

detecting an error between the first feedback signal and the reference signal;

generating a control voltage based on the error; and

controlling a voltage controlled oscillator that generates the first oscillation signal based on the control voltage to adjust the first frequency.

13. The method of claim 12, wherein the feedback signal is a first feedback signal, the error is a first error, the control voltage is a first control voltage, the voltage controlled oscillator is a first voltage controlled oscillator, and generating, by the second PLL circuit, the second oscillation signal having the second frequency with phase locked to the first oscillation signal comprises:

frequency-dividing the first oscillation signal;

frequency-dividing the second oscillation signal to generate a second feedback signal;

detecting a second error between the second feedback signal and the frequency-divided first oscillation signal;

generating a second control voltage based on the second error; and

controlling a second voltage controlled oscillator that generates the second oscillation signal based on the second control voltage to adjust the second frequency.

14. The method of claim 13, further comprising:

frequency-dividing the second oscillation signal.

15. The method of claim 13, further comprising:

adjusting the frequency-divisions for the first oscillation signal and the second oscillation signal to adjust the second frequency.

16. An integrated circuit (IC) chip, comprising a first phase locked loop (PLL) circuit configured to generate a first oscillation signal having a first frequency based on a reference signal having a reference frequency;

a second PLL circuit configured to receive the first oscillation signal and generate a second oscillation signal having a second frequency based on the first oscillation signal; and

a power amplifier configured to operate based on a periodic signal generated based on the second oscillation signal, a frequency difference between the first oscillation signal and the periodic signal being larger than a threshold.

17. The IC chip of claim 16, wherein the first PLL circuit is configured to have a first bandwidth that is smaller than a modulation frequency in the power amplifier and the second PLL circuit is configured to have a second bandwidth that is larger than the modulation frequency in the power amplifier.

18. The IC chip of claim 16, wherein the first PLL circuit comprises:

a divider configured to frequency-divide the first oscillation signal to generate a feedback signal;

an error detecting and controlling circuit configured to detect an error between the feedback signal and the reference signal and generate a control voltage based on the error; and

a voltage controlled oscillator configured to adjust the first frequency based on the control voltage.

19. The IC chip of claim 18, wherein the divider is a first divider, the feedback signal is a first feedback signal, the error detecting and controlling circuit is a first error detecting and controlling circuit, the error is a first error, the control voltage is a first control voltage, the voltage controlled oscillator is a first voltage controlled oscillator, and the second PLL circuit comprises:

a second divider configured to frequency-divide the first oscillation signal;

a third divider configured to frequency-divide the second oscillation signal to generate a second feedback signal;

a second error detecting and controlling circuit configured to detect a second error between the second feedback signal and the frequency-divided first oscillation signal and generate a second control voltage based on the second error; and

a second voltage controlled oscillator configured to adjust the second frequency based on the second control voltage.

20. The IC chip of claim 19, further comprising:

a fourth divider configured to frequency-divide the second oscillation signal to generate the periodic signal.

21. The IC chip of claim 19, further comprising:

a controller configured to control at least one of the first divider, the second divider and the third divider to adjust the second frequency in a range.