System and Method for High Input Capacitive Signal Amplifier

• US 20130271307A1
• Filed: 04/16/2012
• Published: 10/17/2013
• Est. Priority Date: 04/16/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Kropfitsch, Michael, Ceballos, Jose Luis
• Granted Patent: US 8,638,249 B2
• Time in Patent Office: Days
• US Class Current: 341/158
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 2200/555 A voltage generating circuit being realised for biasing different circuit elements
• CPC Class Codes: H03F 2203/45166 Only one input of the dif amp being used for an input signal
• CPC Class Codes: H03F 2203/45526 the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC
• CPC Class Codes: H03F 3/187 in integrated circuits
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03G 3/002 Control of digital or coded signals H03G3/3089 take precedence
• CPC Class Codes: H03G 3/3005 in amplifiers suitable for low-frequencies, e.g. audio amplifiers H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03G 3/3089 Control of digital or coded signals
• CPC Class Codes: H03G 7/002 in untuned or low-frequency amplifiers, e.g. audio amplifiers H03G7/007, H03G7/001, H03G7/008, H03G7/02, H03G7/06 take precedence
• CPC Class Codes: H03G 7/06 having semiconductor devices
• CPC Class Codes: H03G 7/08 incorporating negative feedback
• CPC Class Codes: H03K 5/1532 Peak detectors measuring characteristics of individual pulses G01R29/02
• CPC Class Codes: H03K 5/1536 Zero-crossing detectors in measuring circuits G01R19/175
• CPC Class Codes: H04R 19/04 Microphones H04R19/01 takes precedence
• CPC Class Codes: H04R 2201/003 Mems transducers or their use of the electrostatic type H04R19/005
• CPC Class Codes: H04R 23/00 Transducers other than those covered by groups H04R9/00 - H04R21/00 diaphragms for transducers of the distributed-mode type H04R7/045
• CPC Class Codes: H04R 3/00 Circuits for transducers , loudspeakers or microphones

Abstract

In accordance with an embodiment, a method includes determining an amplitude of an input signal provided by a capacitive signal source, compressing the input signal in an analog domain to form a compressed analog signal based on the determined amplitude, converting the compressed analog signal to a compressed digital signal, and decompressing the digital signal in a digital domain to form a decompressed digital signal. In an embodiment, compressing the analog signal includes adjusting a first gain of an amplifier coupled to the capacitive signal source, and decompressing the digital signal comprises adjusting a second gain of a digital processing block.

Claims

1. A method comprising:

determining an amplitude of an input signal provided by a capacitive signal source;

compressing the input signal in an analog domain to form a compressed analog signal based on the determined amplitude;

converting the compressed analog signal to a compressed digital signal; and

decompressing the digital signal in a digital domain to form a decompressed digital signal, wherein the steps of determining, compressing, converting and decompressing comprises using one or more electronic circuits.

2. The method of claim 1, wherein:

compressing the analog signal comprises adjusting a first gain of an amplifier coupled to the capacitive signal source; and

decompressing the digital signal comprises adjusting a second gain of a digital signal processing block.

3. The method of claim 2, wherein adjusting the first gain of the amplifier comprises adjusting a controllable impedance coupled to an output of the capacitive signal source.

4. The method of claim 2, wherein:

adjusting the first gain of the amplifier comprises setting the first gain to be inversely proportional to the determined amplitude; and

adjusting the second gain of the digital signal processing block comprises setting the second gain to be directly proportional to the determined amplitude.

5. The method of claim 4, wherein the first gain of the amplifier and the second gain of the digital signal processing block is constant below if the determined amplitude is less than a first threshold amplitude.

6. The method of claim 2, wherein:

adjusting the first gain of the amplifier comprises setting the first gain to be inversely proportional to the determined amplitude above a first threshold amplitude; and

adjusting the second gain of the digital signal processing block comprises setting the second gain to be directly proportional to the determined amplitude above the first threshold amplitude.

7. The method of claim 2, wherein:

the digital signal processing block comprises a digital filter; and

adjusting the second gain comprises adjusting filter coefficients of the digital filter.

8. The method of claim 1, further comprising converting the decompressed digital signal to a single bit stream.

9. The method of claim 8, wherein converting the decompressed digital signal comprises using a digital noise shaper.

10. The method of claim 1, wherein determining the amplitude of the input signal comprises:

amplifying or buffering a signal provided by a capacitive signal source to form an amplified signal; and

detecting a peak voltage of the amplified signal.

11. A system for amplifying a signal provided by a capacitive signal source, the system comprising:

a variable gain amplifier comprising an input node configured to be coupled to the capacitive signal source;

an analog to digital converter coupled to an output of the variable gain amplifier;

a digital gain block coupled to an output of the analog to digital converter; and

a gain control circuit configured to

measure an amplitude of an analog signal coupled to the variable gain amplifier,

adjust a first gain of the variable gain amplifier according to a first gain function, and

adjust a second gain of the digital gain block according to a second gain function.

12. The system of claim 11, wherein:

the first gain function defines the first gain as inversely proportional to an amplitude of the signal provided by the capacitive signal source, the second gain function defines the second gain as proportional to the amplitude of the signal provided by the capacitive signal source.

13. The system of claim 11, wherein:

the first gain function defines the first gain as inversely proportional to an amplitude of the signal provided by the capacitive signal source above a first threshold, the second gain function defines the second gain as proportional to the amplitude of the signal provided by the capacitive signal source above the first threshold.

14. The system of claim 13, wherein:

the first gain function further defines the first gain as constant below the first threshold; and

the second gain function further defines the second gain as constant below the first threshold.

15. The system of claim 11, further comprising the capacitive signal source.

16. The system of claim 15, wherein the capacitive signal source comprises a MEMS microphone.

17. The system of claim 11, further comprising a digital noise shaper coupled to an output of the digital gain block.

18. The system of claim 17, wherein the digital noise shaper comprises a one-bit bitstream output.

19. The system of claim 11, wherein:

the digital gain block comprises a digital filter; and

the gain control circuit is configured to adjust the second gain by adjusting filter coefficients of the digital filter.

20. The system of claim 11, wherein the variable gain amplifier, the analog to digital converter, and the gain control circuit is disposed on an integrated circuit.

21. The system of claim 11, wherein the variable gain amplifier comprises a gain setting in which the gain of the variable gain amplifier is less than one.

22. An integrated circuit for amplifying a signal provided by a capacitive signal source, the integrated circuit comprising:

a signal amplifier comprising an input node configured to be coupled to the capacitive signal source;

a peak detector coupled to an output of the signal amplifier;

a gain controller coupled to an output of the peak detector;

a controllable attenuation circuit coupled to the input node of the signal amplifier and to a first gain control signal of the gain controller;

an analog to digital converter coupled to an output of the signal amplifier;

a digital filter coupled to an output of the analog to digital converter; and

a gain coefficient control block coupled to the digital filter and to a second gain control signal of the gain controller, wherein the gain controller is configured to increase an attenuation of the controllable attenuation circuit or decrease a gain of the signal amplifier in response to an increased amplitude of the capacitive signal source and increase a gain of the digital filter in response to the increased amplitude of the capacitive signal source.

23. The integrated circuit of claim 22, wherein the gain controller is configured to increase the attenuation of the controllable attenuation circuit and increase the gain of the digital filter when a signal at the output of the capacitive signal source is above a first threshold amplitude.

24. The integrated circuit of claim 22, wherein the analog to digital converter comprises a sigma-delta analog to digital converter.

25. The integrated circuit of claim 22, wherein the controllable attenuation circuit comprises:

a plurality of capacitors; and

a plurality of switches coupled between the plurality of capacitors and the input of the signal amplifier, the plurality of switches being controllable by the gain controller.

26. The integrated circuit of claim 22, wherein the controllable attenuation circuit provides comprises a controllable input impedance to the signal amplifier.

27. The integrated circuit of claim 22, wherein the signal amplifier comprises a gain of less than one.