OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-ON-PACKAGE STRUCTURES

• US 20130271907A1
• Filed: 08/16/2011
• Published: 10/17/2013
• Est. Priority Date: 08/16/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nickerson, Robert M., Watts, Nicholas R., Mortensen, Russell K.
• Granted Patent: US 10,446,530 B2
• Time in Patent Office: Days
• US Class Current: 361/679.02
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/08238 the bonding area connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48106 the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48245 the item being metallic
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 : Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/107 : Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/43 : Manufacturing methods
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/89 : using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/143 : Digital devices
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/1511 : Structure
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/381 : Pitch distance
• CPC Class Codes: H05K 1/113 : Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 3/4038 : Through-connections; Vertical interconnect access [VIA] connections H05K3/403, H05K3/42 take precedence
• CPC Class Codes: Y10T 29/49124 : On flat or curved insulated base, e.g., printed circuit, etc.

Abstract

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

Claims

1. An interposer, comprising:

a land side including land-side ball-grid array (BGA) including two adjacent, spaced-apart land-side pads, wherein the land-side BGA is configured to interface with a first-level interconnect; and

a package-on-package (POP) side including a POP-side BGA including two adjacent, spaced-apart POP-side pads, wherein the POP-side BGA is configured to interface with a POP interconnect, wherein each of the two land-side pads are coupled respectively to the two POP-side pads through the interposer, and wherein the two land-side pads each have a different footprint than the respective two POP-side pads.

2. The interposer of claim 1, wherein a given land-side pad is coupled to the corresponding POP-side pad by direct contact with a via.

3. The interposer of claim 1, wherein the different footprint of the two land-side pads is exclusive of the footprint of the two POP-side pads.

4. The interposer of claim 1, wherein the different footprint of the two land-side pads is exclusive of the footprint of the two POP-side pads, wherein the two adjacent, spaced-apart land-side pads are configured at a first pitch, wherein the two adjacent, spaced-apart POP-side pads are configured at a second pitch, and wherein the first pitch is smaller than the second pitch.

5. The interposer of claim 1, wherein the different footprint of the two land-side pads is a less than 50 percent overlap.

6. The interposer of claim 1, wherein the different footprint of the two land-side pads is a less than 50 percent overlap, and wherein a given land-side pad is coupled to the corresponding POP-side pad by direct contact with a via.

7. The interposer of claim 1, wherein the different footprint of the two land-side pads is a less than 50 percent overlap, wherein the two adjacent, spaced-apart land-side pads are configured at a first pitch, wherein the two adjacent, spaced-apart POP-side pads are configured at a second pitch, and wherein the first pitch is smaller than the second pitch.

8. The interposer of claim 1, wherein the different footprint of the two land-side pads is a greater than 50 percent overlap.

9. The interposer of claim 1, wherein the different footprint of the two land-side pads is a less than 50 percent overlap, wherein the two adjacent, spaced-apart land-side pads are configured at a first pitch, wherein the two adjacent, spaced-apart POP-side pads are configured at a second pitch, and wherein the first pitch is smaller than the second pitch.

10. The interposer of claim 1, wherein the two adjacent, spaced-apart land-side pads are configured at a first pitch, wherein the two adjacent, spaced-apart POP-side pads are configured at a second pitch, and wherein the first pitch is smaller than the second pitch.

11. The interposer of claim 1, wherein the two adjacent, spaced-apart land-side pads are part of an array of land-side pads that are all configured at a first pitch, wherein the two adjacent, spaced-apart POP-side pads are part of an array of POP-side pads that are all configured at a second pitch, and wherein the first pitch is smaller than the second pitch.

12. The interposer of claim 1, wherein the two adjacent, spaced-apart land-side pads are configured at a first pitch, wherein the two adjacent, spaced-apart POP-side pads are configured at a second pitch, and wherein the first pitch is the same as the second pitch.

13. The interposer of claim 1, wherein the two adjacent, spaced-apart land-side pads are configured at a first pitch, wherein the two adjacent, spaced-apart POP-side pads are configured at a second pitch, and wherein the first pitch is on 0.5 mm centers and the second pitch is on 0.4 mm centers.

14. An interposer, comprising:

a land side including land-side hall-grid array (BGA) including two adjacent, spaced-apart land-side pads, wherein the land-side BGA is configured to interface with a first-level interconnect;

a package-on-package (POP) side including a POP-side BGA including two adjacent, spaced-apart POP-side pads, wherein the POP-side BGA is configured to interface with a POP interconnect, wherein each of the two land-side pads are coupled respectively to the two POP-side pads through the interposer, and wherein the two land-side pads each have a different footprint than the respective two POP-side pads, wherein the two adjacent, spaced-apart land-side pads are configured at a first pitch, wherein the two adjacent, spaced-apart POP-side pads are configured at a second pitch, further including the die-side BGA is arranged with alternating two- and three-pad occurrences and the land-side BGA is arranged only with two-pad occurrences.

15. The interposer of claim 14, wherein the two adjacent, spaced-apart land-side pads are configured at a first pitch, wherein the two adjacent, spaced-apart POP-side pads are configured at a second pitch, further including the die-side BGA is arranged with alternating two- and three-pad occurrences and the land-side BGA is arranged only with two-pad occurrences, and wherein the first pitch is on 0.5 mm centers and the second pitch is on 0.4 mm centers.

16. The interposer of claim 14, wherein the different footprint of the two land-side pads is exclusive of the footprint of the two POP-side pads.

17. The interposer of claim 14, wherein the different footprint of the two land-side pads is exclusive of the footprint of the two POP-side pads, wherein the two adjacent, spaced-apart land-side pads are configured at a first pitch, wherein the two adjacent, spaced-apart POP-side pads are configured at a second pitch, and wherein the first pitch is smaller than the second pitch.

18. The interposer of claim 14, wherein the different footprint of the two land-side pads is a less than 50 percent overlap.

19. A package-on-package (POP) chip package comprising:

an offset interposer including;

a land side including land-side ball-grid array (BGA) including two adjacent, spaced-apart land-side pads, wherein the land-side BGA is configured to interface with a first-level interconnect; and

a package-on-package (POP) side including a POP-side BGA including two adjacent, spaced-apart POP-side pads, wherein the POP-side BGA is configured to interface with a POP interconnect, wherein each of the two land-side pads are coupled respectively to the two POP-side pads through the interposer, and wherein the two land-side pads each have a different footprint than the respective two POP-side pads;

a POP substrate coupled to POP interconnects on the POP-side BGA; and

a microelectronic device disposed on the POP substrate, wherein the microelectronic device is electrically coupled to the offset interposer through the POP substrate.

21. The POP chip package of claim 19, wherein the different footprint of the two land-side pads is exclusive of the footprint of the two POP-side pads.

22. The POP chip package of claim 19, wherein the different footprint of the two land-side pads is exclusive of the footprint of the two POP-side pads, wherein the two adjacent, spaced-apart land-side pads are configured at a first pitch, wherein the two adjacent, spaced-apart POP-side pads are configured at a second pitch, and wherein the first pitch is smaller than the second pitch.

23. The POP chip package of claim 19, wherein the two adjacent, spaced-apart land-side pads are configured at a first pitch, wherein the two adjacent, spaced-apart POP-side pads are configured at a second pitch, further including the die-side BGA is arranged with alternating two- and three-pad occurrences and the land-side BGA is arranged only with two-pad occurrences.

24. The POP chip package of claim 19, wherein the microelectronic device is flip-chip disposed upon the POP substrate.

25. The POP chip package of claim 19, further including:

a first-level interconnect coupled to the land side of the offset interposer; and

an electronic device mounted on the first-level interconnect.

26. The POP chip package of claim 19, further including:

a first-level interconnect coupled to the land side of the offset interposer;

an electronic device mounted on the first-level interconnect; and

a stacked die mounted on the electronic device.

27. The POP chip package of claim 19, further including:

a first-level interconnect coupled to the land side of the offset interposer;

an electronic device mounted on the first-level interconnect; and

a wire-bonded stacked die mounted on the electronic device.

28. The POP chip package of claim 19, further including:

a first-level interconnect coupled to the land side of the offset interposer;

an electronic device mounted on the first-level interconnect; and

a through-silicon via stacked die mounted on the electronic device.

20. The POP chip package 19, wherein a given land-side pad is coupled to corresponding POP-side pad by direct contact with a via.

29. A process of building an offset interposer, comprising:

forming a land side including land-side ball-grid array (BGA) including two adjacent, spaced-apart land-side pads, wherein the land-side BGA is configured to interface with a first-level interconnect; and

forming a package-on-package (POP) side including a POP-side BGA including two adjacent, spaced-apart POP-side pads, wherein the POP-side BGA is configured to interface with a POP interconnect, wherein each of the two land-side pads are coupled respectively to the two POP-side pads through the interposer, and wherein the two land-side pads each have a different footprint than the respective two POP-side pads.

30. The process of claim 29, wherein the different footprint of the two land-side pads is formed to be exclusive of the footprint of the two POP-side pads, wherein the two adjacent, spaced-apart land-side pads are configured at a first pitch, wherein the two adjacent, spaced-apart POP-side pads are configured at a second pitch, and wherein the first pitch is smaller than the second pitch.

31. The process of claim 29, further including a method of assembling the offset interpose to a first-level interconnect.

32. The process of claim 29, further including a method of assembling the offset interposer to a POP substrate.

33. A computer system comprising:

an offset interposer including;

a land side including land-side ball-grid array (BGA) including two adjacent, spaced-apart land-side pads, wherein the land-side BGA is configured to interface with a first-level interconnect; and

a package-on-package (POP) side including a POP-side BGA including two adjacent, spaced-apart POP-side pads, wherein the POP-side BGA is configured to interface with a POP interconnect, wherein each of the two land-side pads are coupled respectively to the two POP-side pads through the interposer, and wherein the two land-side pads each have a different footprint than the respective two POP-side pads;

a POP substrate coupled to POP interconnects on the POP-side BGA;

a microelectronic device disposed on the POP substrate, wherein the microelectronic device is electrically coupled to the offset interposer through the POP substrate;

a first-level interconnect coupled to the offset interposer at the land side;

an electronic device disposed on the first-level interconnect; and

a foundation substrate that supports the first-level interconnect.

34. The computer system of claim 33, wherein the foundation substrate is part of a mobile device.

35. The computer system of claim 33, wherein the foundation substrate is part of a smartphone device.

36. The computer system of claim 33, wherein the foundation substrate is part of a tablet computer device.

37. The computer system of claim 33, wherein the foundation substrate is part of a vehicle.

38. The computer system of claim 33, wherein the foundation substrate is part of a television.