DATA STORAGE DEVICE AND OPERATING METHOD THEREOF

• US 20130275657A1
• Filed: 09/03/2012
• Published: 10/17/2013
• Est. Priority Date: 04/13/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: KIM, Young Ho, KIM, Kyeong Rho, KWAK, Jeong Soon
• Granted Patent: US 8,904,095 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

An operating method of a data storage device including a plurality of nonvolatile memory devices includes the steps of: mapping physical addresses of the nonvolatile memory devices into logical addresses; reflecting environmental factors to remap a physical address into a logical address requested to be accessed; and performing an interleaving operation for the nonvolatile memory devices using the remapped physical address.

Claims

1. An operating method of a data storage device including a plurality of nonvolatile memory devices, comprising the steps of:

mapping physical addresses of the nonvolatile memory devices into logical addresses;

reflecting environmental factors to remap a physical address into a logical address that is requested to be accessed; and

performing an interleaving operation for the nonvolatile memory devices using the remapped physical address.

2. The operating method according to claim 1, wherein the environmental factors comprise operating states of respective nonvolatile memory devices, a page size, positions of programmable pages, and operation characteristics.

3. The operating method according to claim 2, wherein the physical address mapped into the logical address that is requested to be accessed is changed depending on an operating state of a nonvolatile memory device to which the physical address mapped into the logical address requested to be accessed is allocated.

4. The operating method according to claim 3, wherein, when the nonvolatile memory device to which the physical address mapped into the logical address requested to be accessed is allocated is in a busy state, the logical address requested to be accessed is remapped into a physical address allocated to a nonvolatile memory device in a ready state.

5. The operating method according to claim 2, where the environmental factors further comprise a size of data requested to be accessed currently and a size of data which is to be requested to be accessed in the future.

6. The operating method according to claim 5, wherein the size of the data requested to be accessed is compared to a size of programmable pages of the nonvolatile memory devices, creating a comparison result, and

a physical address mapped into a logical address corresponding is to the data requested to be accessed is changed according to the comparison result.

7. The operating method according to claim 6, wherein, when the size of the data requested to be accessed is larger than the size of programmable pages of the nonvolatile memory devices, the logical address corresponding to the data requested to be accessed is remapped into physical addresses of multi-pages comprising two or more pages.

8. The operating method according to claim 7, wherein the two or more pages of the multi-pages are controlled in parallel by a multi-plane operation.

9. The operating method according to claim 5, wherein the size of the data requested to be accessed currently is compared to the size of the data which is to be requested to be accessed in the future, creating a comparison result, and

a physical address mapped into a logical address corresponding to the data requested to be accessed currently is changed according to the comparison result.

10. A data storage device comprising:

a plurality of nonvolatile memory devices; and

a controller configured to control operations of the nonvolatile is memory devices,

wherein the controller maps physical addresses of the nonvolatile memory devices into logical address provided from a host device, remaps a physical address into a logical address requested to be accessed from the host device by reflecting environmental factors of the host device and the nonvolatile memory devices, and performs an interleaving operation for the nonvolatile memory devices using a remapped physical address.

11. The data storage device according to claim 10, wherein the environmental factors comprise operating states of the nonvolatile memory devices, a page size, and positions of programmable pages.

12. The data storage device according to claim 11, wherein the controller determines an operating state of a nonvolatile memory device to which the physical address mapped into the logical address requested to be accessed is allocated, and changes the physical address mapped into the logical address requested to be accessed according to a determination result.

13. The data storage device according to claim 12, wherein, when determining that the nonvolatile memory device to which the physical address mapped into the logical address requested to be accessed is allocated is in a busy state, the controller remaps the is logical address requested to be accessed into a physical address allocated to a nonvolatile memory device in a ready state.

14. The data storage device according to claim 11, wherein the environmental factors further comprise a size of data requested to be accessed currently from the host device and a size of data which is to be requested to be accessed in the future.

15. The data storage device according to claim 14, wherein the controller compares a size of the data requested to be accessed to a size of programmable pages of the nonvolatile memory devices, creating a comparison result, and changes a physical address mapped into a logical address corresponding to the data to be requested to be accessed according to the comparison result.

16. The data storage device according to claim 15, wherein, when determining that the size of the data requested to be accessed is larger than a size of the programmable pages of the nonvolatile memory devices, the controller remaps the logical address corresponding to the data requested to be accessed into physical addresses of multi-pages comprising two or more pages.

17. The data storage device according to claim 16, wherein the multi-pages are included in any one of the nonvolatile memory devices, and

is the controller controls the multi-pages according to a multi-page method such that two or more pages of the multi-pages are operated in parallel.

18. The data storage device according to claim 11, wherein the controller compares the size of data requested to be accessed currently to the size of data which is to be requested to be accessed in the future, creating a comparison result, and changes a physical address mapped into a logical address corresponding to the data requested to be accessed according to the comparison result.

19. The data storage device according to claim 10, wherein the nonvolatile memory devices and the controller are configured as a memory card.

20. The data storage device according to claim 10, wherein the nonvolatile memory devices and the controller are configured as a solid state drive (SSD).