PLATFORM STORAGE HIERARCHY WITH NON-VOLATILE RANDOM ACCESS MEMORY WITH CONFIGURABLE PARTITIONS

• US 20130275661A1
• Filed: 09/30/2011
• Published: 10/17/2013
• Est. Priority Date: 09/30/2011
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Zimmer, Vincent J., Rothman, Michael A., Doran, Mark S.
• Application Number:
  US13/976,909
• Publication Number:
  US 20130275661A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/0653 with centralised address assignment
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/2024 Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy. The NVRAM is byte-addressable by the processor and can be configured into one or more partitions, with each partition implementing a different tier of the platform storage hierarchy. The NVRAM can be used as mass storage that can be accessed without a storage driver.

Claims

1. A method comprising:

receiving, by a computer system, configuration data that defines partitions of address space in a byte-rewritable and byte-erasable non-volatile random access memory (NVRAM), wherein the partitions comprise at least two partitions that implement two different tiers of a platform storage hierarchy of the computer system;

programming a decode table within a processor that is coupled to the NVRAM according to the configuration data; and

decoding an address in a data access request based on the decode table; and

generating an attribute that indicates one of the partitions to be accessed.

2. The method of claim 1, wherein the NVRAM comprises phase change memory (PCM).

3. The method of claim 1, wherein the NVRAM comprises phase change memory and switch (PCMS).

4. The method of claim 1, wherein the partitions includes a first partition implementing system memory and a second partition implementing mass storage.

5. The method of claim 4, wherein the partitions includes one or more additional partitions implementing firmware memory.

6. The method of claim 1, wherein programming the decode table further comprises:

requesting the configuration data from an authorized server via a network connection;

sending credentials to the authorized server;

receiving the configuration data signed by the authorized server;

setting values of status registers according to the configuration data; and

programming the decode table upon reboot of the computer system according to the values of the status registers.

7. The method of claim 1, wherein programming the decode table further comprises:

creating an affinity table accessible by an operating system (OS) of the computer system, wherein the affinity table allows the OS to differentiate between different portions of system memory that are implemented with different technologies.

8. An apparatus comprising:

system memory, at least a portion of which is implemented by a first partition of a byte-rewritable and byte-erasable non-volatile random access memory (NVRAM);

mass storage, at least a portion of which is implemented by a second partition of the NVRAM;

a processor coupled to the NVRAM;

a decode table stored within the processor, the decode table being programmable by configuration data to indicate the sizes of the first partition and the second partition; and

decode logic within the processor to decode an address in a data access request based on the decode table and generate an attribute that indicates one of the first partition and the second partition to be accessed.

9. The apparatus of claim 8, wherein the NVRAM comprises phase change memory (PCM).

10. The apparatus of claim 8, wherein the NVRAM comprises phase change memory and switch (PCMS).

11. The apparatus of claim 8, wherein the partitions includes a first partition implementing system memory and a second partition implementing mass storage.

12. The apparatus of claim 11, wherein the partitions includes one or more additional partitions implementing firmware memory.

13. A system comprising:

system memory, a first portion of which is implemented by a first partition of a byte-rewritable and byte-erasable non-volatile random access memory (NVRAM) and a second portion of which is implemented by dynamic random access memory (DRAM);

mass storage, at least a portion of which is implemented by a second partition of the NVRAM;

a processor coupled to the system memory and the mass storage; and

a decode table stored within the processor, the decode table being programmable by configuration data to indicate the sizes of the first partition and the second partition; and

decode logic within the processor to decode an address in a data access request based on the decode table and generate an attribute that indicates one of the first partition and the second partition to be accessed.

14. The system of claim 13, wherein the NV RAM comprises phase change memory (PCM).

15. The system of claim 13, wherein the NVRAM comprises phase change memory and switch (PCMS).

16. The system of claim 13, wherein the partitions includes a first partition implementing system memory and a second partition implementing mass storage.

17. The system of claim 16, wherein the partitions includes one or more additional partitions implementing firmware memory.