APPARATUS AND METHOD OF IMPROVED EXTRACT INSTRUCTIONS
First Claim
1. An apparatus, comprising:
- instruction execution logic circuitry to execute;
a) a first instruction and a second instruction, where, both said first instruction and said second instruction select a first group of input vector elements from one of multiple first non overlapping sections of respective first and second input vectors, said first group having a first bit width, each of said multiple first non overlapping sections having a same bit width as said first group;
b) a third instruction and a fourth instruction, where, both said third instruction and said fourth instruction select a second group of input vector elements from one of multiple second non overlapping sections of respective third and fourth input vectors, said second group having a second bit width that is larger than said first bit width, each of said multiple second non overlapping sections having a same bit width as said second group;
masking layer circuitry to mask said first and second groups of said first and third instructions at a first granularity, respective resultants produced therewith being respective resultants of said first and third instructions, and, mask said first and second groups of said second and fourth instructions at a second granularity, respective resultants produced therewith being respective resultants of said second and fourth instructions.
1 Assignment
0 Petitions
Accused Products
Abstract
An apparatus is described that includes instruction execution logic circuitry to execute first, second, third and fourth instructions. Both the first instruction and the second instruction select a first group of input vector elements from one of multiple first non overlapping sections of respective first and second input vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction select a second group of input vector elements from one of multiple second non overlapping sections of respective third and fourth input vectors. The second group has a second bit width that is larger than the first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus includes masking layer circuitry to mask the first and second groups of the first and third instructions at a first granularity, where, respective resultants produced therewith are respective resultants of the first and third instructions. The masking circuitry is also to mask the first and second groups of the second and fourth instructions at a second granularity, where, respective resultants produced therewith are respective resultants of the second and fourth instructions.
-
Citations
20 Claims
-
1. An apparatus, comprising:
-
instruction execution logic circuitry to execute; a) a first instruction and a second instruction, where, both said first instruction and said second instruction select a first group of input vector elements from one of multiple first non overlapping sections of respective first and second input vectors, said first group having a first bit width, each of said multiple first non overlapping sections having a same bit width as said first group; b) a third instruction and a fourth instruction, where, both said third instruction and said fourth instruction select a second group of input vector elements from one of multiple second non overlapping sections of respective third and fourth input vectors, said second group having a second bit width that is larger than said first bit width, each of said multiple second non overlapping sections having a same bit width as said second group; masking layer circuitry to mask said first and second groups of said first and third instructions at a first granularity, respective resultants produced therewith being respective resultants of said first and third instructions, and, mask said first and second groups of said second and fourth instructions at a second granularity, respective resultants produced therewith being respective resultants of said second and fourth instructions. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A method, comprising:
-
executing a first instruction including selecting a first group of input vector elements from one of multiple first non overlapping sections of a first input vector, said first group having a first bit width, each of said multiple first non overlapping sections having a same bit width as said first group, and, masking said selected first group at a first granularity; executing a second instruction including selecting a second group of input vector elements from one of multiple second non overlapping sections of a second input vector, said second group having said first bit width, each of said multiple second non overlapping sections of said second input vector having a same bit width as said first group, and, masking said selected second group at a second granularity, said first granularity being finer than said second granularity; executing a third instruction including selecting a third group of input vector elements from one of multiple third non overlapping sections of a third input vector, said third group having a second bit width, each of said multiple third non overlapping sections having a same bit width as said third group, said second bit width larger than said first bit width, and, masking said selected third group at said second granularity; executing a fourth instruction including selecting a fourth group of input vector elements from one of multiple fourth non overlapping sections of a fourth input vector, said fourth group having said second bit width, each of said multiple fourth non overlapping sections of said fourth input vector having a same bit width as said third group, and, masking said fourth group at said first granularity. - View Dependent Claims (9, 10, 11, 12, 13, 14)
-
-
15. An apparatus, comprising:
-
instruction execution logic circuitry to execute; a) a first instruction and a second instruction, where, both said first instruction and said second instruction select, in accordance with first and second respective immediate operands, a first group of input vector elements from one of multiple first non overlapping sections of respective first and second input vectors, said first group having a first bit width, each of said multiple first non overlapping sections having a same bit width as said first group; b) a third instruction and a fourth instruction, where, both said third instruction and said fourth instruction select, in accordance with third and fourth respective immediate operands, a second group of input vector elements from one of multiple second non overlapping sections of respective third and fourth input vectors, said second group having a second bit width that is larger than said first bit width, each of said multiple second non overlapping sections having a same bit width as said second group; masking layer circuitry to mask said first and second groups of said first and third instructions at a first granularity, respective resultants produced therewith being respective resultants of said first and third instructions, and, mask said first and second groups of said second and fourth instructions at a second granularity, respective resultants produced therewith being respective resultants of said second and fourth instructions. - View Dependent Claims (16, 17, 18, 19, 20)
-
Specification