CONTROLLER FOR MANAGING A RESET OF A SUBSET OF THREADS IN A MULTI-THREAD SYSTEM

• US 20130275989A1
• Filed: 04/12/2012
• Published: 10/17/2013
• Est. Priority Date: 04/12/2012
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Xu, Kun, Kramer, David B., Sullivan, Marie J.
• Granted Patent: US 8,924,784 B2
• Time in Patent Office: Days
• US Class Current: 718/104
• CPC Class Codes: G06F 11/1438 Restarting or rejuvenating
• CPC Class Codes: G06F 11/1479 Generic software techniques for error detection or fault masking
• CPC Class Codes: G06F 9/5022 Mechanisms to release resources

Abstract

An integrated circuit device includes a processor core, and a controller. The processor core issues a command intended for a first thread of a plurality of threads. The controller initiates de-allocates hardware resources of the controller that are allocated to the first thread during a thread reset process for the first thread, returns a specified value to the processor core in response to the first command intended for the first thread during the thread reset process, drops responses intended for the first thread from other devices during the thread reset process, completes the thread reset process in response to a determination that all expected responses intended for the first thread have been either received or dropped, and continues to issue requests to other devices in response to commands from other threads of the plurality of threads and processing corresponding responses during the thread reset process.

Claims

1. A method of managing a reset of a first thread of a plurality of threads executed in an integrated circuit (IC) device, the method comprising:

initiating a thread reset process for the first thread in response to detecting a reset request for the first thread, the thread reset process comprising de-allocating hardware resources of a controller that are allocated to the first thread, returning a specified value from the controller to a processor core of the IC device in response to a first command intended for the first thread, and dropping responses intended for the first thread from other devices;

completing the thread reset process in response to determining that all expected responses intended for the first thread have been either received or dropped; and

continuing to issue requests to other devices in response to commands from other threads of the plurality of threads and processing corresponding responses during the thread reset process.

2. The method of claim 1, further comprising:

detecting an under-run event associated with the first thread, wherein the under-run event indicates that a number of the responses intended for the first thread received by the controller exceeds a number of the expected responses intended for the first thread; and

initiating a reset of the controller in response to the detected under-run event.

3. The method of claim 1, further comprising:

issuing a time out event for the thread reset process in response to determining that a specified period of time has elapsed prior to when all of the expected responses intended for the first thread have been received; and

initiating a reset of the controller in response to the time out event.

4. The method of claim 1, further comprising:

returning a value of a first register within the controller to the processor core in response to a second command for the first thread, wherein the second command is directed to the first register and the first command is directed to a second register within the controller.

5. The method of claim 1, wherein the thread reset process comprises:

decrementing a value stored in a register of the controller that is associated with the first thread in response to each dropped response intended for the first thread; and

determining all expected responses intended for the first thread have been either received or dropped comprises determining the value stored in the register has been decremented to a predetermined value.

6. The method of claim 1, wherein performing the reset comprises:

flushing data associated with the first thread from a memory in the controller.

7. The method of claim 1, wherein the controller is an input/output controller.

8. The method of claim 1, wherein the reset request is received from a managing processor core.

9. A method of managing a soft reset of a first thread of a plurality of threads executed in an integrated circuit (IC) device, the method comprising:

receiving, at a controller, a first command associated with the first thread from a processor core in the IC device;

sending a first transmission packet associated with the first command to another device in communication with the IC device;

receiving a first response packet associated with the first transmission packet from the another device;

sending response data within the response packet to the processor core;

initiating a thread reset process for the first thread in response to detecting a reset request for the first thread, the thread reset process comprising de-allocating hardware resources of a controller that are allocated to the first thread, dropping additional response packets associated with the first transmission packet from the another device, decrementing a counter associated with the first thread in response to dropping each of the additional response packets, returning a specified value from the controller to the processor core in response to a second command intended for the first thread, completing the thread reset process in response to determining that the counter is equal to a predetermined value, and continuing to issue requests to other devices in response to commands from other threads of the plurality of threads; and

receiving, at the controller, a third command associated with the first thread from the processor core after the thread reset process is completed; and

sending a second transmission packet associated with the second command to the another device.

10. The method of claim 9, further comprising:

detecting an under-run event associated with the first thread, wherein the under-run event indicates that a number of the responses intended for the first thread received by the controller exceeds a number of the expected responses intended for the first thread; and

initiating a reset of the controller in response to the detected under-run event.

11. The method of claim 9, further comprising:

issuing a time out event for the thread reset process in response to determining that a specified period of time has elapsed prior to when all of the expected responses intended for the first thread have been received; and

initiating a reset of the controller in response to the time out event.

12. The method of claim 9, wherein the thread reset process further comprises:

returning a value of a first register within the controller to the processor core in response to a fourth command for the first thread, wherein the fourth command is directed to a read request of the first register and the second command is directed to a read request of a second register within the controller.

13. The method of claim 9, wherein the counter is equal to a predetermined value when all expected responses intended for the first thread have been either received or dropped.

14. An integrated circuit (IC) device comprising:

at least one processor core, the processor core to issue commands intended for a plurality of threads; and

a controller in communication with the processor core, the controller to initiate thread reset processes for threads in response to detected reset requests for the threads, the controller to de-allocate hardware resources of the controller that are allocated to a thread being reset during a thread reset process, the controller to return a specified value to the processor core to issue the commands to the thread in response to a command intended for the thread being reset during the thread reset process, the controller to drop responses intended for the thread being reset from other devices during the thread reset process, and the controller to complete the thread reset process in response to a determination that all expected responses intended for the thread being reset have been either received or dropped, during the thread reset of the thread the controller to issue requests to other devices in response to commands from other threads of the plurality of threads and the controller to process corresponding responses.

15. The IC device of claim 14, the controller during the reset process further to return a value of a register within the controller to the processor core to issue the commands in response to a second command for the thread, wherein the second command is directed to a read request of the register and the command is directed to a read request of another register within the controller.

16. The IC device of claim 14, wherein the controller comprises:

a memory to store data associated with the thread, the controller to flush data associated with the thread being reset from the memory during the thread reset process of the thread.

17. The IC device of claim 14, the controller to detect an under-run event associated with the thread being reset, wherein an under-run event indicates that a number of the responses intended for the thread being reset received by the controller exceeds a number of the expected responses intended for the thread being reset, and the controller to initiate a reset of the controller in response to the detected under-run event.

18. The IC device of claim 14, the controller further to issue a time out event for the thread reset process in response to determining that a specified period of time has elapsed prior to when all of the expected responses intended for the thread being reset have been received, and the controller to initiate a reset of the controller in response to the time out event.

19. The IC device of claim 14, wherein the controller comprises:

a register associable with the thread being reset to store a value indicating a difference between a number of expected responses intended for the thread being reset and a number of received or dropped responses intended for the thread being reset, the controller further to decrement a value stored in the register in response to each received or dropped response intended for the thread being reset.

20. The IC device of claim 19, a processor core of the at least one processor cores to issue read commands for values stored the register, and the processor core to determine that the thread reset process of the thread being reset is complete in response to a value stored in the register being equal to a predetermined value.

21. The IC device of claim 14, the controller further to reset multiple threads of the plurality of threads without affecting remaining threads of the plurality of threads.