THROUGH SILCON VIA WITH REDUCED SHUNT CAPACITANCE

• US 20130277773A1
• Filed: 09/20/2011
• Published: 10/24/2013
• Est. Priority Date: 09/20/2010
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Bryzek, Janusz, Bloomsburgh, John Gardner, Acar, Cenk
• Granted Patent: US 9,006,846 B2
• Time in Patent Office: Days
• US Class Current: 257/415
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81B 2207/096 through the substrate
• CPC Class Codes: B81B 3/0086 Electrical characteristics, e.g. reducing driving voltage, improving resistance to peak voltage
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: H01G 7/06 having a dielectric selected for the variation of its permittivity with applied voltage, i.e. ferroelectric capacitors electrets H01G7/02

Abstract

This document refers to apparatus and methods for a device layer of a microelectromechanical system (MEMS) sensor having vias with reduced shunt capacitance. In an example, a device layer can include a substrate having a pair of trenches separated in a horizontal direction by a portion of the substrate, wherein each trench of the pair of trenches includes first and second vertical layers including dielectric, the first and second vertical layers separated by a third vertical layer including polysilicon.

Claims

1. A via layer for a MEMS device, the via layer comprising;

a substrate having a pair of trenches separated in a horizontal direction by a portion of the substrate, wherein each trench of the pair of trenches includes first and second vertical layers including a dielectric, the first and second vertical layers separated by a third vertical layer including polysilicon.

2. The via layer of claim 1, wherein less than about 80% of the volume of the third vertical layer includes polysilicon.

3. The via layer of claim 1, wherein less than about 20% of the the volume of the third vertical layer includes polysilicon.

4. The via layer of claim 1, the first and second vertical layers include thermal oxide.

5. The via layer of claim 1, wherein each of the first and second vertical layers of dielectric include thermal oxide and a third material having a dielectric constant lower than the dielectric constant of the thermal oxide.

6. A sensor comprising:

a cap layer;

a device layer, coupled to the cap layer, including a proof mass; and

a via layer coupled to the device layer, wherein the device layer includes;

a silicon substrate having a pair of trenches separated in a horizontal direction by a portion of the silicon substrate,

wherein each trench of the pair of trenches includes first and second vertical layers including a dielectric separated by a third vertical layer including polysilicon.

7. The sensor of claim 6, wherein less than about 80% of the volume of the third vertical layer includes polysilicon.

8. The sensor of claim 6, wherein less than about 20% of the the volume of the third vertical layer includes polysilicon.

9. The sensor of claim 6, the first and second vertical layers include thermal oxide.

10. The sensor of claim 6, wherein each of the first and second vertical layers of dielectric include thermal oxide and a second material having a dielectric constant lower than the dielectric constant of the thermal oxide.