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Bump-on-Trace Interconnect

  • US 20130277830A1
  • Filed: 10/17/2012
  • Published: 10/24/2013
  • Est. Priority Date: 04/18/2012
  • Status: Active Grant
First Claim
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1. A semiconductor device comprising:

  • a first substrate;

    a bump disposed on the first substrate;

    a second substrate;

    a conductive trace disposed on the second substrate and having a sidewall; and

    solder electrically connecting the bump and the conductive trace, wherein the solder covers at least half the height of the sidewall of the conductive trace;

    wherein the bump is separated from the conductive trace by a distance less than the height of the sidewall of the conductive trace.

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