Semiconductor Method and Device of Forming a Fan-Out Device with PWB Vertical Interconnect Units

• US 20130277851A1
• Filed: 06/14/2013
• Published: 10/24/2013
• Est. Priority Date: 03/23/2012
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Limited
• Inventors: Lin, Yaojian, Chen, Kang, Gu, Yu, Marimuthu, Pandi Chelvam
• Granted Patent: US 9,837,303 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24155 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device has a modular interconnect unit or interconnect structure disposed in a peripheral region of the semiconductor die. An encapsulant is deposited over the semiconductor die and interconnect structure. A first insulating layer is formed over the semiconductor die and interconnect structure. A plurality of openings is formed in the first insulating layer over the interconnect structure. The openings have a pitch of 40 micrometers. The openings include a circular shape, ring shape, cross shape, or lattice shape. A conductive layer is deposited over the first insulating layer. The conductive layer includes a planar surface. A second insulating layer is formed over the conductive layer. A portion of the encapsulant is removed to expose the semiconductor die and the interconnect structure. The modular interconnect unit includes a vertical interconnect structure. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.

Claims

1. A method of making a semiconductor device, comprising:

providing a semiconductor die;

disposing a modular interconnect unit adjacent to the semiconductor die;

depositing an encapsulant over the semiconductor die and modular interconnect unit;

forming a first insulating layer over the semiconductor die and modular interconnect unit;

forming a plurality of openings in the first insulating layer over the modular interconnect unit; and

depositing a conductive layer over the first insulating layer.

2. The method of claim 1, wherein the openings include a circular shape, ring shape, cross shape, or lattice shape.

3. The method of claim 2, further including forming a second insulating layer over the conductive layer, wherein the second insulating layer includes a thickness of less than 25 micrometers.

4. The method of claim 1, further including planarizing a surface of the conductive layer.

5. The method of claim 1, wherein the modular interconnect unit includes a vertical interconnect structure electrically connected to the conductive layer.

6. The method of claim 1, further including removing a portion of the encapsulant to expose the semiconductor die and modular interconnect unit.

7. A method of making a semiconductor device, comprising:

providing a semiconductor die;

disposing an interconnect structure in a peripheral region of the semiconductor die;

forming a first insulating layer over the semiconductor die and interconnect structure;

forming a first opening in the first insulating layer over the interconnect structure; and

forming a conductive layer over the first insulating layer.

8. The method of claim 7, further including forming a second insulating layer over the conductive layer, wherein the second insulating layer includes a thickness of less than 25 micrometers.

9. The method of claim 7, wherein the first opening includes a circular shape, ring shape, cross shape, or lattice shape.

10. The method of claim 7, wherein the first opening includes a width of 20 to 30 micrometers.

11. The method of claim 7, further including forming a second opening in the first insulating layer over the interconnect structure.

12. The method of claim 11, wherein a pitch of the first and second openings is 40 micrometers.

13. The method of claim 7, further including:

forming an encapsulant over the semiconductor die and interconnect structure; and

removing a portion of the encapsulant over the interconnect structure.

14. A semiconductor device, comprising:

a semiconductor die;

an interconnect structure disposed in a peripheral region of the semiconductor die;

a first insulating layer including a plurality of openings formed over the interconnect structure; and

a conductive layer formed over the first insulating layer.

15. The semiconductor device of claim 14, wherein a pitch of the openings is 40 micrometers.

16. The semiconductor device of claim 14, wherein the openings include a circular shape, ring shape, cross shape, or lattice shape.

17. The semiconductor device of claim 14, further including a second insulating layer formed over the conductive layer and first insulating layer.

18. The semiconductor device of claim 17, wherein the second insulating layer includes a thickness of less than 25 micrometers.

19. The semiconductor device of claim 14, further including:

an encapsulant formed over the semiconductor die and interconnect structure; and

an opening formed in the encapsulant over the interconnect structure.

20. A semiconductor device, comprising:

a semiconductor die;

an interconnect structure disposed in a peripheral region of the semiconductor die; and

a first insulating layer formed over the semiconductor die and interconnect structure including a first opening over the interconnect structure.

21. The semiconductor device of claim 20, further including a second opening formed in the first insulating layer over the interconnect structure.

22. The semiconductor device of claim 21, wherein a pitch of the first and second openings is 40 micrometers.

23. The semiconductor device of claim 21, wherein the first and second openings include a circular shape, ring shape, cross shape, or lattice shape.

24. The semiconductor device of claim 20, further including:

a conductive layer formed over the first insulating layer; and

a second insulating layer formed over the conductive layer and first insulating layer.

25. The semiconductor device of claim 24, wherein a surface of the conductive layer is planar.