Power Management Integrated Circuit for Driving Inductive Loads

• US 20130278301A1
• Filed: 04/23/2012
• Published: 10/24/2013
• Est. Priority Date: 04/23/2012
• Status: Active Grant

• Current Assignee: Active-Semi, Inc. (Qorvo, Inc.)
• Original Assignee: Active-Semi, Inc. (Qorvo, Inc.)
• Inventors: Huynh, Steven
• Granted Patent: US 10,418,809 B2
• Time in Patent Office: Days
• US Class Current: 327/110
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248
• CPC Class Codes: H03K 17/165 by feedback from the output circuit to the control circuit

Abstract

A power management integrated circuit includes pairs of high-side and low-side drivers, sensing circuitry, and a processor. The high-side and low-side drivers are used in combination with external discrete NFETs to drive multiple windings of a motor. The N-channel LDMOS transistor of each high-side driver has an associated isolation structure and a tracking and clamping circuit. If the voltage on a terminal of the integrated circuit pulses negative during a switching of current flow to the motor, then the isolation structure and tracking and clamping circuit clamps the voltage on the isolation structure and blocks current flow from the substrate to the drain. An associated ESD protection circuit allows the voltage on the terminal to pulse negative. As a result, a large surge of current that would otherwise flow through the high-side driver is blocked, and is conducted outside the integrated circuit through a body diode of an external NFET.

Claims

1. An integrated circuit comprising:

a first terminal;

a second terminal;

a third terminal;

a P-channel field effect transistor, wherein a source of the P-channel transistor is coupled to the first terminal, wherein a drain of the P-channel transistor is coupled to the second terminal;

an N-channel field effect transistor, wherein a drain of the N-channel transistor is coupled to the second terminal, wherein a source of the N-channel transistor is coupled to the third terminal, wherein an N type isolation structure is disposed between a substrate and the drain of the N-channel transistor; and

a tracking and clamping circuit that in a tracking mode provides a relatively low resistance path between the drain and the isolation structure such that when a voltage Vd on the drain is substantially positive that a voltage Viso on the isolation structure tracks Vd, whereas the tracking and clamping circuit in a clamping mode provides a relatively high resistance path between the drain and the isolation structure such that when Vd is substantially negative that Viso is clamped to be no more negative than approximately −

0.7 volts.

2. Integrated circuit of claim 1, wherein the relatively low resistance path has a resistance of less than approximately two thousand ohms, wherein the relatively high resistance path has a resistance of more than approximately two thousand ohms, wherein the relatively low resistance path is provided by the tracking and clamping circuit if Vd is substantially greater than Viso, and wherein the relatively high resistance path is provided by the tracking and clamping circuit if Vd is substantially less than Viso.

3. The integrated circuit of claim 1, wherein both the P-channel transistor and the N-channel transistor are disposed on the substrate, and wherein the isolation structure includes an N type isolation buried layer and an N type isolation sinker that together isolate a P type well region from the substrate.

4. The integrated circuit of claim 1, further comprising:

a level shift circuit that receives a control signal and that supplies a level shifted version of the control signal onto a gate of the N-channel transistor and onto a gate of the P-channel transistor.

5. The integrated circuit of claim 1, further comprising:

an electrostatic discharge (ESD) protection circuit coupled between the third terminal and a ground conductor, wherein the ESD protection circuit cannot conduct an ESD protection current unless the voltage on the third terminal with respect to ground potential on the ground conductor is less than a predetermined negative voltage or is greater than a predetermined positive voltage, wherein the predetermined negative voltage is a negative voltage that is more negative than approximately −

5.0 volts.

6. The integrated circuit of claim 1, wherein the integrated circuit is a power management integrated circuit and includes a processor and a plurality of high-side drivers, wherein the P-channel transistor, the N-channel transistor and the tracking and clamping circuit are parts of one of the high-side drivers.

7. A method comprising:

(a) driving a control signal from a high-side driver onto a first terminal of an integrated circuit, wherein the high-side driver is a part of the integrated circuit, wherein the high-side driver includes an N-channel field effect transistor, wherein a drain of the N-channel field effect transistor is coupled to the first terminal of the integrated circuit, wherein a source of the N-channel field effect transistor is coupled to a second terminal of the integrated circuit, and wherein an N type isolation structure is disposed between the N-channel field effect transistor and a substrate;

(b) in a tracking mode providing a relatively low resistance path between the drain and the isolation structure such that when a voltage Vd on the drain with respect to a voltage Vsub on the substrate is substantially positive that a voltage Viso on the isolation structure tracks Vd; and

(c) in a clamping mode providing a relatively high resistance path between the drain and the isolation structure such that when Vd is substantially negative that Viso is clamped to be no more negative than approximately −

0.7 volts.

8. The method of claim 7, wherein the relatively low resistance path has a resistance of less than approximately two thousand ohms, wherein the relatively high resistance path has a resistance of more than approximately two thousand ohms, wherein the relatively low resistance path is provided by the tracking and clamping circuit if Vd is substantially greater than Viso, and wherein the relatively high resistance path is provided by the tracking and clamping circuit if Vd is substantially less than Viso.

9. The method of claim 8, further comprising:

receiving a control signal and supplying a level shifted version of the control signal onto a gate of the N-channel field effect transistor and onto a gate of the P-channel field effect transistor.

10. The method of claim 7, further comprising:

communicating control information from a processor of the integrated circuit to the high-side driver such that the high-side driver drives a control signal onto the first terminal.

11. An integrated circuit comprising:

a first terminal;

a second terminal;

a third terminal;

a P-channel field effect transistor, wherein a source of P-channel transistor is coupled to the first terminal, wherein a drain of the P-channel transistor is coupled to the second terminal;

an N-channel field effect transistor, wherein a drain of the N-channel transistor is coupled to the second terminal, wherein a source of the N-channel transistor is coupled to the third terminal, wherein an N type isolation structure is disposed between the N-channel transistor and a substrate; and

means for coupling the drain of the N-channel transistor to the isolation structure such that when a voltage Vd on the drain is substantially positive that a voltage Viso on the isolation structure tracks Vd, and for coupling the drain of the N-channel transistor to the isolation structure such that when Vd is substantially negative that Viso is clamped to be no more negative than a predetermined negative voltage.

12. The integrated circuit of claim 11, further comprising:

a level shift circuit that receives a control signal and that supplies a level shifted version of the control signal onto a gate of the N-channel field effect transistor and onto a gate of the P-channel field effect transistor.

13. The integrated circuit of claim 11, wherein the means for coupling allows Viso to track Vd when Vd is substantially positive by providing a relatively low resistance path between the drain of the N-channel transistor and the isolation structure, and wherein the means for coupling provides a relatively high resistance path between the drain of the N-channel transistor and the isolation structure when Viso is clamped to be no more negative than the predetermined negative voltage.

14. The integrated circuit of claim 11, wherein the means for coupling comprises two resistors coupled in series, and wherein the means for coupling further comprises a diode coupled in parallel with one of the two resistors.

15. The integrated circuit of claim 11, wherein the predetermined negative voltage is approximately −

0.7 volts.

16. The integrated circuit of claim 11, wherein the substrate is a P type substrate, and wherein the N type isolation structure comprises an N type buried layer and an N type sinker.

17. The integrated circuit of claim 11, wherein the integrated circuit is a power management integrated circuit and includes a processor and a plurality of high-side drivers, wherein the P-channel transistor, the N-channel transistor and the means for coupling are parts of one of the high-side drivers.

18. A power management integrated circuit comprising:

a plurality high-side drivers and low-side drivers organized in pairs, wherein each of the high-side drivers comprises;

a P-channel field effect transistor;

an N-channel field effect transistor having a drain that is coupled to a drain of the P-channel field effect transistor, wherein the N-channel field effect transistor has a source that is coupled to a terminal of the integrated circuit, wherein an N type isolation structure is disposed between the N-channel transistor and a substrate of the integrated circuit; and

means for coupling the drain to the isolation structure such that when a voltage on the terminal is substantially positive that a voltage Viso on the isolation structure tracks a voltage Vd on the drain, and for coupling the drain and the isolation structure such that when the voltage on the terminal is substantially negative that Viso is clamped to be no more negative than a predetermined negative voltage; and

a processor that outputs control information to the plurality of high-side drivers and low-side drivers and thereby causes the high-side drivers and the low-side drivers to output control signals onto terminals of the integrated circuit.

19. The power management integrated circuit of claim 18, wherein the means prevents a large substrate surge current from flowing through the high-side driver when the voltage on the terminal spikes negative as a result of a switching of an inductive load coupled to the terminal.

20. The power management integrated circuit of claim 18, wherein the means limits a peak magnitude of a surge current flowing through the high-side driver when the voltage on the terminal spikes negative as a result of a switching of an inductive load coupled to the terminal, and wherein the means limits this peak current to have a peak of less than approximately five hundred microamperes.

21. A power management integrated circuit comprising:

a plurality high-side drivers and low-side drivers organized in pairs, wherein each of the high-side drivers comprises;

a P-channel field effect transistor;

an N-channel field effect transistor having a drain that is coupled to a drain of the P-channel field effect transistor, wherein the N-channel field effect transistor has a source that is coupled to a terminal of the integrated circuit, wherein an N type isolation structure is disposed between the N-channel transistor and a substrate of the integrated circuit; and

means coupled to the isolation structure for preventing a large substrate surge current from flowing through the terminal and through the high-side driver when the voltage on the terminal spikes negative as a result of a switching of an inductive load coupled to the terminal; and

a processor that outputs control information to the plurality of high-side drivers and low-side drivers and thereby causes the high-side drivers and the low-side drivers to output control signals onto terminals of the integrated circuit.

22. The power management integrated circuit of claim 21, wherein a voltage Viso on the isolation structure is clamped to a predetermined voltage when the voltage on the terminal spikes negative as a result of the switching.

23. The power management integrated circuit of claim 21, wherein the means provides a resistive current path between the drain of the N-channel field effect transistor and the N type isolation structure.