LEVEL SHIFT CIRCUIT UTILIZING RESISTANCE IN SEMICONDUCTOR SUBSTRATE

• US 20130278319A1
• Filed: 09/09/2011
• Published: 10/24/2013
• Est. Priority Date: 11/25/2010
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Akahane, Masashi
• Granted Patent: US 8,975,944 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 2217/0063 High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
• CPC Class Codes: H03K 3/356182 with additional means for controlling the main nodes

Abstract

A level shift circuit does not affect delay time, regardless of the size of resistor resistance value. The level shift circuit includes first and second series circuits wherein first and second resistors and first and second switching elements are connected in series, rise detector circuits that compare the rise potentials of output signals of the first and second series circuits with a predetermined threshold value, and output first and second output signals, which are pulse outputs of a constant duration, when the threshold value is exceeded, and third and fourth switching elements connected in parallel to the first and second resistors respectively. The gate terminals of the third and fourth switching elements are connected to the rise detector circuits, and the third and fourth switching elements are turned on by the first and second output signals respectively.

Claims

1. A level shift circuit, comprising:

a first series circuit wherein a first resistor in a semiconductor substrate, a first switching element connected to an input terminal for inputting a first level shift input signal, and a first level shift output terminal for outputting a first level shift output signal are connected in series;

a second series circuit wherein a second resistor in a semiconductor substrate, a second switching element connected to an input terminal for inputting a second level shift input signal, and a second level shift output terminal for outputting a second level shift output signal are connected in series;

rise detector circuits, connected to the first series circuit and second series circuit and into which are input the first level shift output signal and second level shift output signal output from the first series circuit and second series circuit respectively, that compare the rising potential of the first level shift output signal and second level shift output signal with a predetermined threshold value, and output a first output signal and second output signal, which are pulse outputs of a constant duration, when the threshold value is exceeded;

a third switching element connected in parallel to the first resistor, wherein a source terminal of the third switching element is connected to a power source potential, a drain terminal of the third switching element is connected to the first level shift output terminal, and a gate terminal of the third switching element is connected to the rise detector circuits; and

a fourth switching element connected in parallel to the second resistor, wherein a source terminal of the fourth switching element is connected to a power source potential, a drain terminal of the fourth switching element is connected to the second level shift output terminal, and a gate terminal of the fourth switching element is connected to the rise detector circuits, wherein

the third switching element is turned on by the first output signal from the rise detector circuits, and the fourth switching element is turned on by the second output signal from the rise detector circuits.

2. The level shift circuit according to claim 1, wherein the first resistor and second resistor are parasitic resistors in the semiconductor substrate.

3. The level shift circuit according to claim 1, further comprising:

a logic circuit that outputs a third output signal when either of the first output signal or second output signal is output from the rise detector circuits, wherein

a dead time is provided for input times of the first level shift input signal and second level shift input signal, an output pulse width of the rise detector circuits is equal to or less than the dead time, and the third switching element and fourth switching element are turned on when the third output signal is output.

4. The level shift circuit according to claim 1, further comprising:

a latch malfunction protection circuit, into which the first level shift output signal and second level shift output signal are input, that outputs a high impedance signal when both the first level shift output signal and second level shift output signal are at an L level; and

a latch circuit, into which an output from the latch malfunction protection circuit is input, that stores and outputs a value of the output from the latch malfunction protection circuit when the output from the latch malfunction protection circuit is at an L or H level and, when the output from the latch malfunction protection circuit is of a high impedance, holds a value stored immediately before the input reaches the high impedance, and outputs the stored value together with an inverse signal of the stored value, wherein

one output terminal of the latch circuit is connected via a first feedback resistor to the first level shift output terminal, and the other output terminal is connected via a second feedback resistor to the second level shift output terminal.

5. The level shift circuit according to claim 1, further comprising:

a first feedback transistor connected in parallel to the first resistor and a second feedback transistor connected in parallel to the second resistor, wherein a gate of the first feedback transistor is connected to the second level shift output terminal, and a gate of the second feedback transistor is connected to the first level shift output terminal.

6. The level shift circuit according to claim 2, further comprising:

a logic circuit that outputs a third output signal when either of the first output signal or second output signal is output from the rise detector circuits, wherein

a dead time is provided for input times of the first level shift input signal and second level shift input signal, an output pulse width of the rise detector circuits is equal to or less than the dead time, and the third switching element and fourth switching element are turned on when the third output signal is output.

7. The level shift circuit according to claim 2, further comprising:

a latch malfunction protection circuit, into which the first level shift output signal and second level shift output signal are input, that outputs a high impedance signal when both the first level shift output signal and second level shift output signal are at an L level; and

a latch circuit, into which an output from the latch malfunction protection circuit is input, that stores and outputs a value of the output from the latch malfunction protection circuit when the output from the latch malfunction protection circuit is at an L or H level and, when the output from the latch malfunction protection circuit is of a high impedance, holds a value stored immediately before the input reaches the high impedance, and outputs the stored value together with an inverse signal of the stored value, wherein

one output terminal of the latch circuit is connected via a first feedback resistor to the first level shift output terminal, and the other output terminal is connected via a second feedback resistor to the second level shift output terminal.

8. The level shift circuit according to claim 3, further comprising:

a latch malfunction protection circuit, into which the first level shift output signal and second level shift output signal are input, that outputs a high impedance signal when both the first level shift output signal and second level shift output signal are at an L level; and

a latch circuit, into which an output from the latch malfunction protection circuit is input, that stores and outputs a value of the output from the latch malfunction protection circuit when the output from the latch malfunction protection circuit is at an L or H level and, when the output from the latch malfunction protection circuit is of a high impedance, holds a value stored immediately before the input reaches the high impedance, and outputs the stored value together with an inverse signal of the stored value, wherein

one output terminal of the latch circuit is connected via a first feedback resistor to the first level shift output terminal, and the other output terminal is connected via a second feedback resistor to the second level shift output terminal.

9. The level shift circuit according to claim 2, further comprising:

a first feedback transistor connected in parallel to the first resistor and a second feedback transistor connected in parallel to the second resistor, wherein a gate of the first feedback transistor is connected to the second level shift output terminal, and a gate of the second feedback transistor is connected to the first level shift output terminal.

10. The level shift circuit according to claim 3, further comprising:

a first feedback transistor connected in parallel to the first resistor and a second feedback transistor connected in parallel to the second resistor, wherein a gate of the first feedback transistor is connected to the second level shift output terminal, and a gate of the second feedback transistor is connected to the first level shift output terminal.

11. The level shift circuit according to claim 4, further comprising:

a first feedback transistor connected in parallel to the first resistor and a second feedback transistor connected in parallel to the second resistor, wherein a gate of the first feedback transistor is connected to the second level shift output terminal, and a gate of the second feedback transistor is connected to the first level shift output terminal.

12. An apparatus, comprising:

a first signal output device configured to output a first level shifting signal;

a second signal output device configured to output a second level shifting signal;

wherein the first level shifting signal and the second level shifting signal are to control an output switching element of a high potential side of an output device comprising a power source and a load;

a first detector device configured to compare the first level shifting signal to a reference signal and output a first comparison result signal; and

a second detector device configured to compare the second level shifting signal to the reference signal and output a second comparison result signal;

wherein the first comparison result signal and first comparison result signal are configured to at least partly control switching of the first level shifting signal and the second level shifting signal based at least in part on the presence of a parasitic resistance.

13. The apparatus of claim 12, wherein at least one of the first detector device or the second detector device comprises:

a comparator having the reference signal and one of the first level shifting signal or the second level shifting signal as inputs; and

a delay device having one of the first level shifting signal or the second level shifting signal as an input.

14. The apparatus of claim 13, wherein at least one of the first detector device or the second detector device further comprises a logic device having an output of the comparator and an output of the delay device as inputs.