METAL-INSULATOR-METAL CAPACITORS ON GLASS SUBSTRATES

• US 20130278568A1
• Filed: 04/24/2012
• Published: 10/24/2013
• Est. Priority Date: 04/24/2012
• Status: Active Grant

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Lasiter, Jon Bradley, Shenoy, Ravindra V., Kidwell, Donald William
• Granted Patent: US 8,896,521 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G02B 26/001 based on interference in an adjustable optical cavity interference filters G02B5/28; devices or arrangements using multiple reflections in spectrometry or monochromators G01J3/26
• CPC Class Codes: H01G 4/008 Selection of materials
• CPC Class Codes: H01G 4/06 Solid dielectrics
• CPC Class Codes: H01G 4/30 Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/15 Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/0306 : Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/115 : Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 1/182 : associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
• CPC Class Codes: Y10T 29/49124 : On flat or curved insulated base, e.g., printed circuit, etc.

Abstract

This disclosure provides systems, methods, and apparatus for metal-insulator-metal capacitors on glass substrates. In one aspect, an apparatus may include a glass substrate, with the glass substrate defining at least one via in the glass substrate. A first electrode layer may be disposed over surfaces of the glass substrate, including surfaces of the at least one via. A dielectric layer may be disposed on the first electrode layer. A second electrode layer may be disposed on the dielectric layer, with the dielectric layer electrically isolating the first electrode layer from the second electrode layer.

Claims

1. An apparatus comprising:

a glass substrate, the glass substrate defining at least one first via in the glass substrate;

a first electrode layer disposed over surfaces of the glass substrate, including surfaces of the at least one first via;

a dielectric layer disposed on the first electrode layer; and

a second electrode layer disposed on the dielectric layer, the dielectric layer electrically isolating the first electrode layer from the second electrode layer.

2. The apparatus of claim 1, further comprising:

a dielectric adhesion layer disposed on the surfaces of the glass substrate, including the surfaces of the at least one first via, wherein the first electrode layer is disposed on the dielectric adhesion layer.

3. The apparatus of claim 2, wherein the dielectric adhesion layer includes an oxide.

4. The apparatus of claim 1, wherein the glass substrate includes a photoimageable glass.

5. The apparatus of claim 1, wherein the glass substrate is about 50 microns to 1.1 millimeters thick.

6. The apparatus of claim 1, wherein the at least one first via defines an opening on a surface of the glass substrate of about 2 microns to 200 microns.

7. The apparatus of claim 1, wherein the glass substrate defines a plurality of vias.

8. The apparatus of claim 7, wherein each via of the plurality of vias has a hexagonal cross section.

9. The apparatus of claim 1, wherein the first electrode layer and the second electrode layer include copper.

10. The apparatus of claim 1, wherein the first electrode layer, the dielectric layer, and the second electrode layer form a capacitor, the capacitor having a capacitance density of at least about 200 nanofarads per square millimeter.

11. The apparatus of claim 1, wherein the at least one first via in the glass substrate is a through glass via.

12. The apparatus of claim 1, wherein the at least one first via in the glass substrate is a blind via.

13. The apparatus of claim 1, the glass substrate further defining at least one second through glass via in the glass substrate.

14. The apparatus of claim 13, further comprising:

a conductive material covering a surface of the at least one second through glass via to electrically connect a first electronic component above the glass substrate to a second electronic component below the glass substrate.

15. The apparatus of claim 14, further comprising:

an interposer between the first and second electronic components, the interposer including the glass substrate and at least one of the first electrode layer and the second electrode layer.

16. The apparatus of claim 1, further comprising:

a second dielectric layer disposed on the second electrode layer; and

a third electrode layer disposed on the second dielectric layer, the second dielectric layer electrically isolating the second electrode layer from the third electrode layer.

17. A system comprising the apparatus of claim 1, the system further comprising:

a display;

a processor that is configured to communicate with the display, the processor being configured to process image data; and

a memory device that is configured to communicate with the processor.

18. The system of claim 17, further comprising:

a driver circuit configured to send at least one signal to the display; and

a controller configured to send at least a portion of the image data to the driver circuit.

19. The system of claim 17, further comprising:

an image source module configured to send the image data to the processor.

20. The system of claim 19, wherein the image source module includes at least one of a receiver, transceiver, and transmitter.

21. The system of claim 17, further comprising:

an input device configured to receive input data and to communicate the input data to the processor.

22. An apparatus comprising:

a glass substrate, the glass substrate defining at least one via in the glass substrate;

a first electrode layer disposed over surfaces of the glass substrate, including surfaces of the at least one via;

a second electrode layer; and

means for electrically isolating the first electrode layer from the second electrode layer.

23. The apparatus of claim 22, further comprising:

means for improving adhesion of the first electrode layer to the surfaces of the glass substrate.

24. The apparatus of claim 22, wherein the glass substrate further includes means for electrically connecting a first electronic component above the glass substrate to a second electronic component below the glass substrate.

25. A method comprising:

forming at least one via in a glass substrate;

depositing a first electrode layer over surfaces of the glass substrate, including surfaces of the at least one via;

depositing a dielectric layer on the first electrode layer; and

depositing a second electrode layer on the dielectric layer.

26. The method of claim 25, further comprising:

depositing a dielectric adhesion layer on the surfaces of the glass substrate, including the surfaces of the at least one via, wherein the first electrode layer is deposited on the dielectric adhesion layer.

27. The method of claim 26, wherein the dielectric adhesion layer is deposited using an atomic layer deposition process.

28. The method of claim 25, wherein the glass substrate includes a photoimageable glass, and wherein forming the at least one via in the photoimageable glass substrate includes:

exposing an area of the photoimageable glass substrate where the at least one via is to be formed to ultraviolet light;

exposing the photoimageable glass substrate to an elevated temperature; and

etching the at least one via in the photoimageable glass substrate with an acid.

29. The method of claim 25, wherein forming the at least one via in the glass substrate includes at least one of a sandblasting process and a laser ablation process.

30. The method of claim 25, wherein each of depositing the first electrode layer and depositing the second electrode layer include:

depositing a seed layer with at least one of a chemical vapor deposition process, an atomic layer deposition process, and an electroless plating process; and

plating a metal on the seed layer.

31. The method of claim 25, further comprising:

forming at least one through glass via in the glass substrate, wherein forming the at least one via and the at least one through glass via are performed substantially simultaneously.