DYNAMICALLY CONFIGURABLE MLC STATE ASSIGNMENT

• US 20130279252A1
• Filed: 06/17/2013
• Published: 10/24/2013
• Est. Priority Date: 06/10/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Fernandes, Brandon Lee
• Granted Patent: US 8,830,752 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/5646 Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

Memory devices facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device is capable of inverting the lower page bit values of a complete page of MLC memory cells when a count of the lower page data values is equal to or greater than a particular value or a comparison of current levels compared with a reference current level is equal to or exceeds some threshold condition.

Claims

1. A memory device, comprising:

a plurality of memory cells comprising a page of memory cells, wherein each memory cell of the page is configured to store data comprising an upper page and a lower page; and

control circuitry;

wherein the control circuitry is configured to determine whether data is to be read from the upper page or the lower page in response to a read request; and

wherein the control circuitry is configured to determine whether data read from the lower page should be inverted before outputting that data.

2. The memory device of claim 1, wherein the control circuitry is further configured to determine whether an inversion flag, corresponding to the data read from the lower page, is set to determine whether data read from the lower page should be inverted before outputting that data.

3. The memory device of claim 2, wherein the control circuitry is configured to output the data read from the lower page after inverting that data if the inversion flag is set or to output the data read from the lower page without inverting that data if the inversion flag is not set.

4. The memory device of claim 2, wherein the control circuitry is further configured to determine whether the inversion flag is set in parallel with reading the data from the lower page.

5. The memory device of claim 1, wherein the control circuitry is further configured to output the data read from the upper page without determining whether that data should be inverted before output.

6. A memory device, comprising:

a plurality of memory cells comprising a page of memory cells at each of first and second locations within the memory device, wherein each memory cell of each page is configured to store data comprising an upper page and a lower page; and

control circuitry;

wherein the control circuitry is configured to determine whether data is to be read from one of the upper page or the lower page at the first location upon generation of an internal command; and

wherein the control circuitry is configured to determine whether data read from the one of the upper page or the lower page at the first location that is to be programmed into the lower page at the second location should be inverted using an inversion operation before programming the data read from the one of the upper page or the lower page at the first location into the lower page at the second location.

7. The memory device of claim 6, wherein the control circuitry is further configured to program data read from the other one of the upper page or the lower page at the first location into the upper page at the second location without determining whether that data should be inverted.

8. The memory device of claim 6, wherein the control circuitry is configured to determine whether the data read from the upper page or the lower page at the first location that is to be programmed into the lower page at the second location should be inverted in response to determining how many zeros there are in that data.

9. The memory device of claim 8, wherein the control circuitry is further configured to perform the inversion operation on the data read from the upper page or the lower page at the first location that is to be programmed into the lower page at the second location to invert that data, before programming that data into the lower page at the second location, in response to the number of zeros being equal to or exceeding a threshold number, and to subsequently program the inverted data into the lower page at the second location, and wherein the control circuitry is further configured to program the data read from the upper page or the lower page at the first location that is to be programmed into the lower page at the second location into the lower page at the second location without inverting that data in response to the number of zeros being less than the threshold number.

10. The memory device of claim 6, wherein the control circuitry is further configured to determine whether the data read from the upper page or the lower page at the first location is to be programmed into the lower page or an upper page at the second location before determining whether that data should be inverted using the inversion operation, and wherein if the data is to be read from the lower page at the first location, the control circuitry is further configured to determine whether that data was previously inverted, before determining whether that data is to be programmed into the lower page or an upper page at the second location.

11. The memory device of claim 10, wherein the control circuitry is further configured to determine whether an inversion flag is set to determine that the data to be read from the lower page at the first location was previously inverted.

12. The memory device of claim 11, wherein if the data read from the lower page at the first location was previously inverted, the control circuitry is further configured to invert the previously inverted data before determining whether that data is to be programmed into the lower page or the upper page at the second location.

13. A memory device, comprising:

a plurality of memory cells comprising a page of memory cells, wherein each memory cell of the page is configured to store data comprising an upper page and a lower page; and

control circuitry;

wherein the control circuitry is configured to determine whether data is to be read from the upper page or the lower page in response to a read request;

wherein the control circuitry is configured to read an inversion flag corresponding to data read from the lower page concurrently with reading the lower page; and

wherein the control circuitry is configured to determine, in response to a value of the inversion flag, whether data read from the lower page should be inverted before outputting that data.

14. The memory device of claim 13, wherein the control circuitry is configured to output the data read from the lower page after inverting that data if the inversion flag has a first value, and to output the data read from the lower page without inverting that data if the inversion flag has a second value different from the first value.

15. The memory device of claim 13, wherein the control circuitry is further configured to output the data read from the upper page without determining whether that data should be inverted before output.

16. A memory device, comprising:

a plurality of memory cells comprising a page of memory cells at each of first and second locations within the memory device, wherein each memory cell of each page is configured to store data comprising an upper page and a lower page;

control circuitry; and

a data cache;

wherein the data cache is configured to generate a plurality of currents in response to data stored in the data cache;

wherein the control circuitry is configured to determine whether data is to be read from one of the upper page or the lower page at the first location upon generation of an internal command;

wherein the control circuitry is configured to store the data read from the one of the upper page or the lower page at the first location to the data cache before programming the cached data to one of the upper page or the lower page at the second location;

wherein the control circuitry is configured, if the cached data is to be programmed to the lower page at the second location, to determine whether the cached data should be inverted using an inversion operation before programming the cached data into the lower page at the second location; and

wherein the control circuitry is configured to determine whether the cached data should be inverted in response to a cumulative current measurement of the plurality of currents generated in response to the cached data.

17. The memory device of claim 16, wherein the control circuitry is further configured, if the cached data is to be programmed to the upper page at the second location, to program the cached data into the upper page at the second location without determining whether the cached data should be inverted.

18. The memory device of claim 16, wherein the control circuitry is further configured to determine that the cached data should be inverted before programming the cached data into the lower page at the second location if the cumulative current measurement exceeds a reference current.

19. The memory device of claim 16, wherein the control circuitry is further configured to determine whether the data read from the upper page or the lower page at the first location is to be programmed into the upper page or the lower page at the second location before determining whether the cached data should be inverted, and wherein if the data is to be read from the lower page at the first location, the control circuitry is further configured to determine whether that data was previously inverted, before determining whether that data is to be programmed into the upper page or the lower page at the second location.

20. The memory device of claim 19, wherein the control circuitry further configured to determine whether an inversion flag is set to determine that the data to be read from the lower page at the first location was previously inverted.