SEMICONDUCTOR MEMORY STORAGE APPARATUS HAVING CHARGE STORAGE LAYER AND CONTROL GATE

• US 20130279254A1
• Filed: 03/15/2013
• Published: 10/24/2013
• Est. Priority Date: 04/23/2012
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KAMATA, Yoshihiko, TABATA, Koji, HAMANO, Tomoyuki, KOGA, Mitsuhiro, YOKOTA, Yuko
• Application Number:
  US13/839,219
• Publication Number:
  US 20130279254A1
• Time in Patent Office: Days
• US Class Current: 365/185.09
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check

Abstract

According to one embodiment, a semiconductor memory storage apparatus includes an array, a sense amplifier, and a controller. The array includes a memory cell. The sense amplifier includes a first latch and a second latch. The first latch and the second latch are capable of storing a data read out from the memory cell. The controller performs a first operation, a second operation, and a third operation. In the first operation, the controller transfers an inverted data in the first latch to the first node and transfers the data in the second latch. In the second operation, the controller transfers the data in the first latch to the first node and transfers an inverted data in the second latch.

Claims

1. A semiconductor memory storage apparatus comprising:

a memory cell array including a memory cell;

a sense amplifier configured to include a first latch and a second latch, the first latch and the second latch being capable of storing a data read out from the memory cell; and

a controller configured to perform a first operation, a second operation, and a third operation, the controller performing the first operation and the second operation by using the data read out from the memory cell and data supplied from outside, the controller outputting a first result in the first operation, the controller outputting a second result in the second operation, thereafter performing a third operation based on a first result and a second result,

wherein in the first operation, the controller transfers an inverted data in the first latch to the first node and transfers the data in the second latch,

in the second operation, the controller transfers the data in the first latch to the first node and transfers an inverted data in the second latch.

2. The apparatus of claim 1, wherein the sense amplifier includes n number of sense units, and

the controller sequentially performs the third operation to the sense units.

3. The apparatus of claim 2, wherein the memory cell array has a first area including system information,

the data read from the memory cell array includes a first data and an expected value, the first data being input to and output from the outside via the sense amplifier, and the expected value being a value stored in the first area and read out from the memory cell, and

the first operation and the second operation by the sense amplifier uses the first data and the expected value.

4. The apparatus of claim 3, further comprising:

an ECC controller configured to make the second latch store the second data if any erroneous read exists in the data by determining whether or not the data is erroneously read at the reading time,

wherein the controller performs the third operation by the data stored in the first latch and the second data.

5. The apparatus of claim 1, wherein the detector may transfer the result obtained by the third operation to the first latch.

6. The apparatus of claim 2, wherein the detector may transfer the result obtained by the third operation to the first latch.

7. The apparatus of claim 2, wherein

The sense units include a first sense unit and a second sense unit adjacent to the first sense unit,

the first sense unit and the second sense unit each includes a first MOS transistor, the first MOS transistor transferring the data output to and input from the outside,

the first node of the first sense unit electrically connects to the first latch through the first MOS transistor.

8. The apparatus of claim 7, wherein

the controller turns on the first MOS transistor and transfers the data held by the first latch to the first node in the second sense unit, while the controller outputs H-level busy signal to the outside.

9. An operation method of a semiconductor memory storage apparatus including a memory cell array comprising:

reading data from a memory cell in the memory cell array, and storing the data in a first latch;

storing an expected value to the second latch, the expected value being stored a first area in the memory array and being a value expected to be read from the memory cell;

transferring first data obtained by inverting the expected value to a detector via a first node, thereafter transferring second data obtained by inverting the data to the detector via the second node, and setting a value of the detector to third data;

transferring a value corresponded to the third data to a third latch via the first node; and

setting a value of the detector to fourth data, thereafter transferring the expected value to detector via the first node, by transferring the expected value to the first node and transferring a value corresponding to a potential level of the first node to the detector.

10. The method of claim 9, wherein,

the detector, the first latch and the second latch are included in respective sense amplifiers which read the data from the memory cell, and

transfer to the third latch from the first latch and the second latch is sequentially performed to each of the sense amplifiers.

11. The method of claim 9, further comprising:

determining whether or not the data is erroneously read at the reading time, and storing fifth data in the second latch if any erroneous read exists in the data,

wherein a correction process is performed by the data which is stored in the first latch, and the fifth data.

12. The method of claim 10, further comprising:

determining whether or not the data is erroneously read at the reading time, and storing fifth data in the second latch if any erroneous read exists in the data,

wherein a correction process is performed by the data which is stored in the first latch, and the fifth data.

13. An operation method of semiconductor memory storage apparatus including a memory cell array comprising:

reading data from a memory cell in a memory cell array, and storing the read data in a first latch via a first node;

transferring an expected value being expected to be read from the memory cell, to the first node from a second latch in which the expected value is stored;

evacuating the read data stored in the first latch to an evacuation circuit;

performing a first operation by transferring the expected value stored in the first node to the first latch; and

performing a second operation by transferring the read data evacuated to the evacuation circuit to the first node holding the expected value.

14. The method of claim 13, wherein

to evacuate the read data stored in the first latch to the evacuation circuit is,

each of a first MOS transistor and a second MOS transistor which capable of connecting the first latch and the evacuation circuit is turned on, the first MOS transistor inputs and outputs the read data to and from the first latch, and the second MOS transistor is connected in series to the first MOS transistor.

15. The method of claim 14, wherein

to transfer of the expected value stored in the first node to the first latch is,

each of a third MOS transistor and the first MOS transistor which capable of connecting the first node and the first latch is turned on, and the third MOS transistor outputs inverted data of the first node to the first latch.

16. The method of claim 15, wherein

an execution of the second operation turns on a fourth MOS transistor which inputs and outputs the read data to and from the evacuation circuit, the second MOS transistor and a fifth MOS transistor which is connected at one end to the first node and may be grounded at the other end, the fourth MOS transistor, the second MOS transistor and the fifth MOS transistor being capable of connecting the evacuation circuit and the first node.

17. The method of claim 16, wherein

the third operation operates inverted data of the first result, and inverted data of the second result.

18. The method of claim 17, wherein

the third operation turns on a sixth MOS transistor which transfers the first result stored in the first node to the first latch, and a seventh MOS transistor which is connected in series to the sixth MOS transistor and inputs and outputs the inverted data to and from the first latch.

19. The method of claim 13, wherein

a plurality of sense amplifiers sensing the held data read out of the memory cell are arranged,

the first node and the first latch are provided in each of the sense amplifiers, and

the first evacuation circuit is the first node in the adjacent sense amplifier.

20. The method of claim 13, wherein

the first evacuation circuit is a bit line which may be electrically connected to the first node.