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Erase Operation For 3D Non-Volatile Memory With Controllable Gate-Induced Drain Leakage Current

  • US 20130279257A1
  • Filed: 04/18/2012
  • Published: 10/24/2013
  • Est. Priority Date: 04/18/2012
  • Status: Active Grant
First Claim
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1. A method for performing an erase operation in a 3D stacked non-volatile memory device, comprising:

  • performing each erase iteration of a plurality of erase iterations of the erase operation for a set of memory cells in at least one NAND string, the at least one NAND string comprises a drain-side end in communication with a bit line, and a select gate, drain (SGD) transistor, the SGD transistor comprises a drain in communication with the drain-side end, and the SGD transistor comprises a control gate, the performing each erase iteration comprising;

    raising a voltage of the bit line from a starting level (Vss) to an intermediate level (Vgidl);

    raising the voltage of the bit line from the intermediate level (Vgidl) to a peak level (Verase);

    when the voltage of the bit line is at the starting level and at the intermediate level, controlling the control gate of the SGD transistor to provide a gate-to-drain voltage of the SGD transistor which is sufficiently high to generate gate-induced drain leakage (GIDL) current in the at least one NAND string; and

    stepping up the intermediate level in at least one erase iteration of the plurality of erase iterations.

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