Erase Operation For 3D Non-Volatile Memory With Controllable Gate-Induced Drain Leakage Current
First Claim
1. A method for performing an erase operation in a 3D stacked non-volatile memory device, comprising:
- performing each erase iteration of a plurality of erase iterations of the erase operation for a set of memory cells in at least one NAND string, the at least one NAND string comprises a drain-side end in communication with a bit line, and a select gate, drain (SGD) transistor, the SGD transistor comprises a drain in communication with the drain-side end, and the SGD transistor comprises a control gate, the performing each erase iteration comprising;
raising a voltage of the bit line from a starting level (Vss) to an intermediate level (Vgidl);
raising the voltage of the bit line from the intermediate level (Vgidl) to a peak level (Verase);
when the voltage of the bit line is at the starting level and at the intermediate level, controlling the control gate of the SGD transistor to provide a gate-to-drain voltage of the SGD transistor which is sufficiently high to generate gate-induced drain leakage (GIDL) current in the at least one NAND string; and
stepping up the intermediate level in at least one erase iteration of the plurality of erase iterations.
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Accused Products
Abstract
An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.
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Citations
22 Claims
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1. A method for performing an erase operation in a 3D stacked non-volatile memory device, comprising:
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performing each erase iteration of a plurality of erase iterations of the erase operation for a set of memory cells in at least one NAND string, the at least one NAND string comprises a drain-side end in communication with a bit line, and a select gate, drain (SGD) transistor, the SGD transistor comprises a drain in communication with the drain-side end, and the SGD transistor comprises a control gate, the performing each erase iteration comprising; raising a voltage of the bit line from a starting level (Vss) to an intermediate level (Vgidl); raising the voltage of the bit line from the intermediate level (Vgidl) to a peak level (Verase); when the voltage of the bit line is at the starting level and at the intermediate level, controlling the control gate of the SGD transistor to provide a gate-to-drain voltage of the SGD transistor which is sufficiently high to generate gate-induced drain leakage (GIDL) current in the at least one NAND string; and stepping up the intermediate level in at least one erase iteration of the plurality of erase iterations. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A 3D stacked non-volatile memory device, comprising:
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a bit line; a set of memory cells in at least one NAND string, the at least one NAND string comprises a drain-side end in communication with the bit line, and a select gate, drain (SGD) transistor, the SGD transistor comprises a drain in communication with the drain-side end, and the SGD transistor comprises a control gate; and a control circuit, the control circuit, to perform each erase iteration of a plurality of erase iterations of an erase operation for a set of memory cells;
raises a voltage of the bit line from a starting level (Vss) to an intermediate level (Vgidl);
raises the voltage of the bit line from the intermediate level (Vgidl) to a peak level (Verase);
when the voltage of the bit line is at the starting level and at the intermediate level, controls the control gate of the SGD transistor to provide a gate-to-drain voltage of the SGD transistor which is sufficiently high to generate gate-induced drain leakage (GIDL) current in the at least one NAND string; and
the control circuit steps up the intermediate level in at least one erase iteration of the plurality of erase iterations. - View Dependent Claims (15, 16, 17, 18)
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19. A method for performing an erase operation in a 3D stacked non-volatile memory device, comprising:
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performing an erase iteration of a plurality of erase iterations of the erase operation for a set of memory cells in at least one NAND string, the performing the erase iteration comprises raising a voltage of a bit line in communication with the at least one NAND string from a starting level (Vss) to an intermediate level (Vgidl), raising the voltage of the bit line from the intermediate level (Vgidl) to a peak level (Verase); performing a verify test for the set of memory cells; determining whether a verify condition is met based on the verify test, the verify condition indicating a progress of the set of memory cells in the erase operation; if the verify condition is met, stepping up the intermediate level in a next erase iteration of the plurality of erase iterations; and if the verify condition is not met, not stepping up the intermediate level in the next erase iteration of the plurality of erase iterations. - View Dependent Claims (20, 21, 22)
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Specification