MEMORY DEVICES AND MEMORY CONTROLLERS

• US 20130279283A1
• Filed: 01/03/2013
• Published: 10/24/2013
• Est. Priority Date: 04/24/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Chul-Woo Park, Eun-Sung Seo, Hong-Sun Hwang
• Inventors: PARK, Chul-Woo, HWANG, Hong-Sun, SEO, Eun-Sung
• Granted Patent: US 9,978,430 B2
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413

Abstract

A memory system includes at least one memory device and a memory controller. The at least one memory device includes a refresh request circuit that generates refresh request signals at timings based on data retention times of memory cells, such as based on individual data retention times of a memory cell row. The memory controller schedules operation commands for the at least one memory device in response to the received refresh request signals.

Claims

1-26. -26. (canceled)

27. A memory device, comprising:

a memory cell array including a plurality of rows of memory cells;

a refresh request circuit configured to issue requests for refresh operations to an external device; and

control logic configured to receive commands from the external device and control the memory device in accordance with the received commands,

wherein the refresh request circuit is configured to issue a request for a refresh operation for a first row of memory cells to the external device, and the control logic is configured to receive a first refresh command to refresh the first row from the external device and cause a refresh operation of the first row of memory cells in response to the first request command.

28. The memory device of claim 27, wherein the refresh request circuit is configured to issue requests for refresh operations for a plurality of first rows of memory cells of the memory device at a first refresh rate and issue requests for refresh operations for a plurality of second rows of memory cells of the memory device at one or more second refresh rates, each of the one or more second refresh rates being higher than the first refresh rate.

29. The memory device of claim 28,

wherein the refresh request circuit comprises a lookup table configured to store addresses of the plurality of second rows of memory cells at table entries of the lookup table, and

wherein a sequential access of the entries of the lookup table determines a timing of issuance of requests for refresh operations for the second rows of memory cells.

30. The memory device of claim 29,

wherein the lookup table is configured to store addresses of the plurality of first rows of memory cells at table entries of the lookup table, and

wherein sequential access of the entries of the lookup table determine a timing of issuance of requests for refresh operations for the first rows of memory cells.

31. The memory device of claim 29,

wherein the refresh request circuit comprises an address counter configured to generate sequential addresses of the memory of the memory cells, including addresses of the first and second rows of memory cells, the refresh request circuit configured to issue requests for refresh operations for rows of memory cells identified by the sequential addresses generated by the address counter.

32. The memory device of claim 31, further comprising a multiplexer, the multiplexer configured to select sequential addresses generated by the address counter and addresses of the plurality of second rows output by the lookup table and provide the selected address for output to the external device.

33. The memory device of claim 29, further comprising a lookup table pointer generator configured to output and regularly change a table pointing signal used to access a table entry of the lookup table corresponding to the table pointing signal.

34. The memory device of claim 33,

wherein the lookup table includes empty table entries between table entries containing addresses of second rows of memory cells acting to regulate a timing between a sequential output of the addresses of the second rows of memory cells.

35. The memory device of claim 33,

wherein entries of the lookup table include wait information, and

wherein a timing of a change of the lookup table pointer is responsive to the wait information.

36. The memory device of claim 33,

wherein entries of the lookup table include wait information, and

wherein a timing of a change of the lookup table pointer from identifying a first entry of the lookup table to identifying a second entry of the lookup table is responsive to wait information stored with the first entry of the lookup table.

45. A memory system comprising the memory device of claim 27 and the memory controller connected to the memory device to provide commands to the memory device.

37. A memory controller comprising:

a command generator configured to generate memory commands in response to command requests from a host;

a scheduler configured to generate a command queue providing a sequential list of memory commands to be issued to a memory device; and

a storage unit configured to store one or more addresses of the memory device received with a refresh request from a refresh request circuit,

wherein the scheduler is configured to alter a first sequential list of memory commands in the command queue to insert refresh commands into the command queue corresponding to the one or more addresses of the memory device stored in the storage unit.

38. The memory controller of claim 37, wherein the storage unit is configured to store non-sequential addresses of the memory device to provide different refresh rates for different memory locations of the memory device.

39. The memory controller of claim 37, wherein the scheduler is configured to provide refresh commands for first rows of memory cells at a first rate and provide refresh commands for second rows of memory cells at one or more second rates, the second rates being higher than the first rate.

40. The memory controller of claim 37, further comprising a buffer configured to receive the one or more addresses of the memory device from a refresh request circuit external to the memory controller.

41. The memory controller of claim 40, further comprising a data mask pin configured to receive the refresh request from the refresh request circuit external to the memory controller.

42. The memory controller of claim 37, further comprising the refresh request circuit.

43-44. -44. (canceled)

46-47. -47. (canceled)