Highly Integrated Media Access Control

• US 20130279523A1
• Filed: 06/14/2013
• Published: 10/24/2013
• Est. Priority Date: 09/27/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Denney, Lisa Voigt, Moshar, Hooman, Lansing, Shane Patrick, Nazareth, Sean Francis, Pantelias, Niki Roberta, Horton, John Daniel
• Granted Patent: US 8,934,503 B2
• Time in Patent Office: Days
• US Class Current: 370/474
• CPC Class Codes: H04L 12/2801 Broadband local area networks
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/52 by attributing bandwidth to queues
• CPC Class Codes: H04L 47/6215 Individual queue per QOS, rate or priority
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04N 7/17309 Transmission or handling of upstream communications

Abstract

A supervisory communications device, such as a headend device within a communications network, monitors and controls communications with a plurality of remote communications devices throughout a widely distributed network. The supervisory device allocates bandwidth on the upstream channels by sending MAP messages over its downstream channel. A highly integrated media access controller integrated circuit (MAC IC) operates within the headend to provide lower level processing on signals exchanged with the remote devices. The enhanced functionality of the MAC IC relieves the processing burden on the headend CPU and increases packet throughput.. The enhanced functionality includes header suppression and expansion. DES encryption and decryption, fragment reassembly, concatenation, and DMA operations.

Claims

1. An apparatus to process an ingress signal within a media access controller integrated circuit (MAC IC), comprising:

an ingress processor configured to format the ingress signal for delivery of information data to a destination node, the ingress processor including;

a direct memory access unit configured to receive the ingress signal from a memory; and

a downstream processor configured to format the received ingress signal according to a transmission protocol associated with the destination node to provide a formatted signal, the downstream processor including;

a payload header suppressor configured to receive a packet header along with the ingress signal, and to suppress the packet header based on information included in the ingress signal; and

a header processor configured to create a new header based on the information.