METHODS OF FORMING BULK FINFET DEVICES SO AS TO REDUCE PUNCH THROUGH LEAKAGE CURRENTS

• US 20130280883A1
• Filed: 04/24/2012
• Published: 10/24/2013
• Est. Priority Date: 04/24/2012
• Status: Active Grant

• Current Assignee: Tessera Advanced Technologies Inc (Adeia Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Faul, Juergen, Jakubowski, Frank
• Granted Patent: US 9,023,715 B2
• Time in Patent Office: Days
• US Class Current: 438/434
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Abstract

Disclosed are methods of forming bulk FinFET semiconductor devices to reduce punch through leakage currents. One example includes forming a plurality of trenches in a semiconducting substrate to define a plurality of spaced-apart fins, forming a doped layer of insulating material in the trenches, wherein an exposed portion of each of the fins extends above an upper surface of the doped layer of insulating material while a covered portion of each of the fins is positioned below the upper surface of the doped layer of insulating material, and performing a process operation to heat at least the doped layer of insulating material to cause a dopant material in the doped layer to migrate from the doped layer of insulating material into the covered portions of the fins and thereby define a doped region in the covered portions of the fins that is positioned under the exposed portions of the fins.

Claims

1. A method of forming a FinFET device, comprising:

forming a plurality of trenches in a semiconducting substrate to thereby define a plurality of spaced-apart fins in a semiconducting substrate;

forming a doped layer of insulating material in said trenches, wherein an exposed portion of each of said fins extends above an upper surface of said doped layer of insulating material while a covered portion of each of said fins is positioned below said upper surface of said doped layer of insulating material; and

performing at least one process operation to heat at least said doped layer of insulating material to cause a dopant material in said doped layer of insulating material to migrate from said doped layer of insulating material into said covered portions of said fins and thereby define a doped region in said covered portions of said fins that is positioned under said exposed portions of said fins.

2. The method of claim 1, wherein forming said doped layer of insulating material comprises introducing said dopant material into said layer of insulating material by performing an in situ doping process whereby said dopant material is introduced into said doped layer of insulating material as it is being formed.

3. The method of claim 1, wherein forming said doped layer of insulating material comprising:

depositing an undoped layer of insulating material; and

performing at least one ion implantation process to introduce said dopant material into said undoped layer of insulating material.

4. The method of claim 1, wherein forming said doped layer of insulating material comprises:

performing an in situ doping deposition process to form said doped layer of insulating material to a thickness such that it overfills said trenches; and

performing an etching process to reduce said thickness of said doped layer of insulating material such that said upper surface of said doped layer of insulating material is positioned at a level that is below a level of an upper surface of each of said fins.

5. The method of claim 1, wherein said FinFET device is an N-type FinFET device and wherein said doped layer of insulating material is doped with a P-type dopant.

6. The method of claim 5, wherein said doped layer of insulating material is boron silicate glass (BSG).

7. The method of claim 1, wherein said FinFET device is a P-type FinFET device and wherein said doped layer of insulating material is doped with an N-type dopant.

8. The method of claim 7, wherein said doped layer of insulating material is phosphorus silicate glass (PSG).

9. The method of claim 1, wherein said doped layer of insulating material has a dopant concentration of about 10²²-10²³ ion/cm³.

10. The method of claim 1, wherein said doped region in said covered portions of said fins has a dopant concentration of about 10¹⁹-10²¹ ion/cm³.

11. The method of claim 1, wherein said doped region in said covered portions of said fins extends along an entire axial length of each of said fins.

12. The method of claim 1, wherein said doped region in said covered portions of said fins is formed at a position wherein a gate structure for said device will be formed thereabove.

13. A method of forming a FinFET device, comprising:

forming a plurality of trenches in a semiconducting substrate to thereby define a plurality of spaced-apart fins in a semiconducting substrate;

performing an in situ doping deposition process to form a doped layer of insulating material in said trenches, said doped layer of insulating material comprising a dopant material;

performing an etching process to reduce a thickness of said doped layer of insulating material such that an upper surface of said doped layer of insulating material is positioned at a level that is below a level of an upper surface of each of said fins, wherein an exposed portion of each of said fins extends above said upper surface of said doped layer of insulating material while a covered portion of each of said fins is positioned below said upper surface of said doped layer of insulating material; and

performing at least one process operation to heat at least said doped layer of insulating material to cause said dopant material in said doped layer of insulating material to migrate from said doped layer of insulating material into said covered portions of said fins and thereby define a doped region in said covered portions of said fins that is positioned under said exposed portions of said fins.

14. The method of claim 13, wherein said FinFET device is an N-type FinFET device and wherein said doped layer of insulating material is doped with a P-type dopant.

15. The method of claim 14, wherein said doped layer of insulating material is boron silicate glass (BSG).

16. The method of claim 13, wherein said FinFET device is a P-type FinFET device and wherein said doped layer of insulating material is doped with an N-type dopant.

17. The method of claim 16, wherein said doped layer of insulating material is phosphorus silicate glass (PSG).

18. The method of claim 13, wherein said doped layer of insulating material has a dopant concentration of about 10²²-10²³ ion/cm³.

19. The method of claim 13, wherein said doped region in said covered portions of said fins has a dopant concentration of about 10¹⁹-10²¹ ion/cm³.

20. The method of claim 13, wherein said doped region in said covered portions of said fins extends along an entire axial length of each of said fins.

21. A method of forming a FinFET device, comprising:

forming a plurality of trenches in a semiconducting substrate to thereby define a plurality of spaced-apart fins in a semiconducting substrate;

forming a doped liner layer of insulating material in said trenches;

performing an etching process to consume a portion of said doped liner layer and thereby define a recessed doped liner layer of insulating material having an upper surface that is positioned at a level that is below a level of an upper surface of each of said fins, wherein an exposed portion of each of said fins extends above said upper surface of said doped liner layer of insulating material while a covered portion of each of said fins is positioned below said upper surface of said doped liner layer of insulating material; and

performing at least one process operation to heat at least said doped liner layer of insulating material to cause a dopant material in said doped liner layer of insulating material to migrate from said doped liner layer of insulating material into said covered portions of said fins and thereby define a doped region in said covered portions of said fins that is positioned under said exposed portions of said fins.

22. The method of claim 21, wherein forming said doped liner layer of insulating material comprises introducing said dopant material into said doped liner layer of insulating material by performing an in situ doping process whereby said dopant material is introduced into said doped liner layer of insulating material as it is being formed.

23. The method of claim 21, wherein forming said doped liner layer of insulating material comprises:

depositing an undoped liner layer of insulating material; and

performing at least one ion implantation process to introduce said dopant material into said undoped liner layer of insulating material.

24. The method of claim 21, further comprising, prior to performing said etching process, depositing an undoped layer of insulating material in said trenches above said doped liner layer of insulating material, and wherein said etching process also consumes a portion of said undoped layer of insulating material.

25. The method of claim 21, wherein said FinFET device is an N-type FinFET device and wherein said doped liner layer of insulating material is doped with a P-type dopant.

26. The method of claim 25, wherein said doped liner layer of insulating material is boron silicate glass (BSG).

27. The method of claim 21, wherein said FinFET device is a P-type FinFET device and wherein said doped liner layer of insulating material is doped with an N-type dopant.

28. The method of claim 27, wherein said doped liner layer of insulating material is phosphorus silicate glass (PSG).

29. The method of claim 21, wherein said doped liner layer of insulating material has a dopant concentration of about 10²²-10²³ ion/cm³.

30. The method of claim 21, wherein said doped region in said covered portions of said fins has a dopant concentration of about 10¹⁹-10²¹ ion/cm³.

31. The method of claim 21, wherein said doped region in said covered portions of said fins extends along an entire axial length of each of said fins.

32. The method of claim 21, wherein said doped region in said covered portions of said fins is formed at a position wherein a gate structure for said device will be formed thereabove.

33. A method of forming a FinFET device, comprising:

forming a plurality of trenches in a semiconducting substrate to thereby define a plurality of spaced-apart fins in a semiconducting substrate;

performing an in situ doping deposition process to form a doped liner layer of insulating material in said trenches, said doped liner layer of insulating material comprising a dopant material;

depositing an undoped layer of insulating material in said trenches above said doped liner layer of insulating material;

performing an etching process to consume a portion of said doped liner layer and said undoped layer of insulating material to thereby define a recessed doped liner layer of insulating material and a recessed undoped layer of insulating material, said recessed doped liner layer of insulating material having an upper surface that is positioned at a level that is below a level of an upper surface of each of said fins, wherein an exposed portion of each of said fins extends above said upper surface of said doped liner layer of insulating material while a covered portion of each of said fins is positioned below said upper surface of said doped liner layer of insulating material; and

performing at least one process operation to heat at least said doped liner layer of insulating material to cause a dopant material in said doped liner layer of insulating material to migrate from said doped liner layer of insulating material into said covered portions of said fins and thereby define a doped region in said covered portions of said fins that is positioned under said exposed portions of said fins.

34. The method of claim 33, wherein said FinFET device is an N-type FinFET device and wherein said doped liner layer of insulating material is doped with a P-type dopant.

35. The method of claim 34, wherein said doped liner layer of insulating material is boron silicate glass (BSG).

36. The method of claim 33, wherein said FinFET device is a P-type FinFET device and wherein said doped liner layer of insulating material is doped with an N-type dopant.

37. The method of claim 36, wherein said doped liner layer of insulating material is phosphorus silicate glass (PSG).

38. The method of claim 33, wherein said doped liner layer of insulating material has a dopant concentration of about 10²²-10²³ ion/cm³.

39. The method of claim 33, wherein said doped region in said covered portions of said fins has a dopant concentration of about 10¹⁹-10²¹ ion/cm³.

40. The method of claim 33, wherein said doped region in said covered portions of said fins extends along an entire axial length of each of said fins.