STORAGE CONTROL DEVICE, MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM AND STORAGE CONTROL METHOD

• US 20130282993A1
• Filed: 03/08/2013
• Published: 10/24/2013
• Est. Priority Date: 04/24/2012
• Status: Active Grant

• Current Assignee: Sony Semiconductor Solutions Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Nakanishi, Kenichi, Tsutsui, Keiichi, Fujinami, Yasushi, Adachi, Naohiro, Okubo, Hideaki, Shinbashi, Tatsuo, Ishii, Ken
• Granted Patent: US 9,152,416 B2
• Time in Patent Office: Days
• US Class Current: 711/155
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A storage control device includes a first rewriting section, a second rewriting section, and a first retry control section. The first rewriting section performs first rewrite to rewrite other of two binary values into a memory cell in which one of the two binary values is written. The second rewriting section performs second rewrite to rewrite the one of the two binary values into the memory cell in which the other of the two binary values is written. The first retry control section causes the memory cell that has undergone the first rewrite to be subjected to the second rewrite followed by the first rewrite again if an error occurs during the first rewrite.

Claims

1. A storage control device comprising:

a first rewriting section adapted to perform first rewrite to rewrite other of two binary values into a memory cell in which one of the two binary values is written;

a second rewriting section adapted to perform second rewrite to rewrite the one of the two binary values into the memory cell in which the other of the two binary values is written; and

a first retry control section adapted to cause the memory cell that has undergone the first rewrite to be subjected to the second rewrite followed by the first rewrite again if an error occurs during the first rewrite.

2. The storage control device according to claim 1 further comprising:

a second retry control section adapted to cause the memory cell that has undergone the second rewrite to be subjected to the first rewrite followed by the second rewrite if an error occurs during the second rewrite.

3. The storage control device according to claim 2, wherein

the memory cell is a variable resistance element in which one of two resistance states, demarcated by a given boundary resistance value, is associated with the one of the two values, and the other resistance state is associated with the other of the two values,

the first rewriting section reads data from the memory cell with respect to a first resistance value set to the other resistance state by the boundary resistance value and determines that the error has occurred if the data value is not the other of the two values, and

the second rewriting section reads data from the memory cell with respect to a second resistance value set to the one of the two resistance states by the boundary resistance value and determines that the error has occurred if the data value is not the one of the two values.

4. The storage control device according to claim 3 further comprising:

a defective cell determination section adapted to determine whether the memory cell is defective based on the number of times the error has been detected in each of the first and second rewriting sections.

5. The storage control device according to claim 3, wherein

the first rewriting section reads first data from the memory cell that has undergone the second rewrite with respect to the first resistance value and performs the first rewrite if the first data value is the one of the two values, and

the second rewriting section reads second data from the memory cell that has undergone the first rewrite with respect to the second resistance value and performs the second rewrite if the second data value is the other of the two values.

6. The storage control device according to claim 3, wherein

the first rewriting section reads not only the first data from the memory cell that has undergone the second rewrite with respect to the first resistance value but also third data with respect to the boundary resistance threshold and performs the first rewrite if the first and third data values are different, and

the second rewriting section reads not only second data from the memory cell that has undergone the first rewrite with respect to the second resistance value but also the third data and performs the second rewrite if the second and third data values are different.

7. A memory system comprising:

a storage control device; and

a first command issuance section adapted to issue the given command if the first error occurs,

the storage control device including

a first rewriting section adapted to perform first rewrite to rewrite other of two binary values into a memory cell in which one of the two binary values is written,

a second rewriting section adapted to perform second rewrite to rewrite the one of the two binary values into the memory cell in which the other of the two binary values is written, and

a retry control section adapted to cause the memory cell that has undergone the first rewrite to be subjected to the second rewrite followed by the first rewrite again in accordance with a given command if an error occurs during the first rewrite.

8. A memory system comprising:

a storage control device; and

a first retry control section adapted to cause the memory cell that has undergone the first rewrite to be subjected to the second rewrite followed by the first rewrite again if an error occurs during the first rewrite,

the storage control device including

a first rewriting section adapted to perform first rewrite to rewrite other of two binary values into a memory cell in which one of the two binary values is written, and

a second rewriting section adapted to perform second rewrite to rewrite the one of the two binary values into the memory cell in which the other of the two binary values is written.

9. An information processing system comprising:

a storage control device; and

a host computer adapted to issue the given command if the first error occurs,

the storage control device including

a first rewriting section adapted to perform first rewrite to rewrite other of two binary values into a memory cell in which one of the two binary values is written,

a second rewriting section adapted to perform second rewrite to rewrite the one of the two binary values into the memory cell in which the other of the two binary values is written, and

a retry control section adapted to cause the memory cell that has undergone the first rewrite to be subjected to the second rewrite followed by the first rewrite again in accordance with a given command if an error occurs during the first rewrite.

10. An information processing system comprising:

a storage control device; and

a host computer adapted to cause the memory cell that has undergone the first rewrite to be subjected to the second rewrite followed by the first rewrite again if an error occurs during the first rewrite,

the storage control device including

a first rewriting section adapted to perform first rewrite to rewrite other of two binary values into a memory cell in which one of the two binary values is written, and

a second rewriting section adapted to perform second rewrite to rewrite the one of the two binary values into the memory cell in which the other of the two binary values is written.

11. A storage control method comprising:

performing first rewrite to rewrite other of two binary values into a memory cell in which one of the two binary values is written;

performing second rewrite to rewrite the one of the two binary values into the memory cell in which the other of the two binary values is written; and

causing the memory cell that has undergone the first rewrite to be subjected to the second rewrite followed by the first rewrite again if an error occurs during the first rewrite.