APPARATUS AND METHOD OF IMPROVED INSERT INSTRUCTIONS

• US 20130283021A1
• Filed: 12/23/2011
• Published: 10/24/2013
• Est. Priority Date: 12/23/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Lurgi GmbH (GEA Group AG)
• Inventors: Ould-Ahmed-Vall, Elmoustapha, Valentine, Robert, Corbal, Jesus, Toll, Bret L., Charney, Mark J., Sperber, Zeev, Gradstein, Amit
• Granted Patent: US 9,619,236 B2
• Time in Patent Office: Days
• US Class Current: 712/226
• CPC Class Codes: G06F 12/0615 Address space extension
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3802 Instruction prefetching

Abstract

An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.

Claims

1. An apparatus, comprising:

instruction execution logic circuitry to execute;

a) a first instruction and a second instruction, where, both said first instruction and said second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors, said first group having a first bit width, each of said multiple first non overlapping sections having a same bit width as said first group;

b) a third instruction and a fourth instruction, where, both said third instruction and said fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors, said second group having a second bit width that is larger than said first bit width, each of said multiple second non overlapping sections having a same bit width as said second group;

masking layer circuitry to mask said first and third instructions at a first resultant vector granularity, and, mask said second and fourth instructions at a second resultant vector granularity.

2. The apparatus of claim 1 wherein said second group is twice as large as said first group.

3. The apparatus of claim 2 wherein said first group is 128 bits and said second group is 256 bits.

4. The apparatus of claim 1 wherein said first granularity is 32 bits and said second granularity is 64 bits.

5. The apparatus of claim 1 wherein said resultant is 512 bits.

6. The apparatus of claim 1 wherein said vector elements are floating point data values.

7. The apparatus of claim 1 wherein said masking layer circuitry permits an element in a destination vector to remain if the element'"'"'s location is masked.

8. A method, comprising:

executing a first instruction including inserting a first group of input vector elements to one of multiple first non overlapping sections of a first resultant vector, said first group having a first bit width, each of said multiple first non overlapping sections having a same bit width as said first group, masking said first group at a first granularity;

executing a second instruction including inserting a second group of input vector elements to one of multiple second non overlapping sections of a second resultant vector, said second group having a second bit width, each of said multiple second non overlapping sections having a same bit width as said second group, masking said second group a second granularity, said first granularity being finer than said second granularity;

executing a third instruction including inserting a third group of input vector elements to one of multiple third non overlapping sections of a third resultant vector, said third group having said first bit width, each of said multiple third non overlapping sections having a same bit width as said first group, masking said third group at said second granularity; and

,

executing a fourth instruction including inserting a fourth group of input vector elements to one of multiple fourth non overlapping sections of a fourth resultant vector, said fourth group having said second bit width, each of said multiple fourth non overlapping sections having a same bit width as said second group, masking said fourth group at said first granularity.

9. The method of claim 8 wherein said first, second, third and fourth instructions are executed by a same execution unit within an instruction execution pipeline.

10. The method of claim 8 wherein said second group is twice as large as said first group.

11. The method of claim 10 wherein said first group is 128 bits and said second group is 256 bits.

12. The method of claim 8 wherein said first granularity is 32 bits and said second granularity is 64 bits.

13. The method of claim 8 wherein respective resultant vectors of said first, second, third and fourth instructions are 512 bits.

14. The method of claim 8 wherein said vector elements are floating point data values.

15. The method of claim 8 wherein said masking includes either of:

i) permitting an element in a destination vector to remain if the element'"'"'s location is masked;

ii) overwriting an element in a destination vector with a fixed value if the element'"'"'s location is masked.

16. An apparatus, comprising:

instruction execution logic circuitry to execute;

a) a first instruction and a second instruction, where, both said first instruction and said second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors in accordance with first and second immediate operands respectively, said first group having a first bit width, each of said multiple first non overlapping sections having a same bit width as said first group;

b) a third instruction and a fourth instruction, where, both said third instruction and said fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors in according with third and fourth immediate operands respectively, said second group having a second bit width that is larger than said first bit width, each of said multiple second non overlapping sections having a same bit width as said second group;

masking layer circuitry to mask said first and third instructions at a first resultant vector granularity, and, mask said second and fourth instructions at a second resultant vector granularity.

17. The apparatus of claim 16 wherein said second group is twice as large as said first group.

18. The apparatus of claim 17 wherein said first group is 128 bits and said second group is 256 bits.

19. The apparatus of claim 16 wherein said first granularity is 32 bits and said second granularity is 64 bits.

20. The apparatus of claim 16 wherein said resultant is 512 bits.