STRAINED STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE STRAINED STRUCTURE

• US 20130285153A1
• Filed: 06/04/2012
• Published: 10/31/2013
• Est. Priority Date: 04/25/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LEE, Tsung-Lin, YEH, Chih Chieh, YUAN, Feng, WANN, Clement Hsingjen, PENG, Cheng-Yi
• Granted Patent: US 9,171,929 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

An exemplary structure for a field effect transistor (FET) comprises a silicon substrate comprising a first surface; a channel portion over the first surface, wherein the channel portion has a second surface at a first height above the first surface, and a length parallel to first surface; and two source/drain (S/D) regions on the first surface and surrounding the channel portion along the length of the channel portion, wherein the two S/D regions comprise SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn, or III-V material.

Claims

1. A field effect transistor (FET) comprising:

a silicon substrate comprising a first surface;

a channel portion over the first surface, wherein the channel portion has a second surface at a first height above the first surface, and a length parallel to first surface; and

two source/drain (S/D) regions on the first surface and surrounding the channel portion along the length of the channel portion, wherein the two S/D regions comprise SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn, or III-V material.

2. The FET of claim 1, wherein a portion of the two S/D regions extending downward from the second surface has a second height equal to or greater than the first height.

3. The FET of claim 2, wherein a ratio of the second height to the first height is from 1 to 1.2.

4. The FET of claim 1, wherein the FET comprise planar FET.

5. The FET of claim 1, wherein the FET comprise FinFET.

6. A semiconductor device comprising:

a silicon substrate comprising a first surface;

a first channel portion and a second channel portion over the first surface, wherein each channel portion has a second surface at a first height above the first surface, and a length parallel to first surface;

a first field effect transistor (FET) comprising first two source/drain (S/D) regions on the first surface and surrounding the first channel portion along the length of the first channel portion, wherein the first two S/D regions comprise SiGe, Ge, GeSn, SiGeSn, SiSn, or III-V material; and

a second FET comprising second two S/D regions on a third surface and surrounding the second channel portion along the length of the second channel portion, wherein the third surface is between the first surface and second surface, wherein the second two S/D regions comprise SiGe, Si, or SiC.

7. The semiconductor device of claim 6, a portion of the first two S/D regions extending downward from the second surface has a second height equal to or greater than the first height.

8. The semiconductor device of claim 7, wherein a ratio of the second height to the first height is from 1 to 1.2.

9. The semiconductor device of claim 6, wherein a portion of the second two S/D regions extending downward from the second surface has a third height less than the first height.

10. The semiconductor device of claim 9, wherein a ratio of the third height to the first height is from 0.5 to 0.9.

11. The semiconductor device of claim 6, wherein the first FET and second FET comprise planar FET.

12. The semiconductor device of claim 6, wherein the first FET and second FET comprise FinFET.

13. The semiconductor device of claim 6, wherein the first FET is a p-type FET and the second FET is an n-type FET.

14. The semiconductor device of claim 6, wherein the first FET is a core device and the second FET is an I/O device.

15-20. -20. (canceled)

21. A semiconductor device comprising:

a substrate comprising a first surface;

a first field effect transistor (FET) on the first surface, the first FET comprising;

a first channel portion over the first surface,

first source/drain (S/D) regions on the substrate surrounding the first channel portion along a length of the first channel portion, the first S/D regions having a first height; and

a second FET on the first surface, the second FET comprising;

a second channel portion over the first surface,

second S/D regions on the substrate surrounding the second channel portion along a length of the second channel portion, the second S/D regions having a second height different from the first height.

22. The semiconductor device of claim 21, wherein a portion of the second channel portion is positioned between the first surface and the second S/D regions.

23. The semiconductor device of claim 21, wherein the first channel portion has a channel height above the first surface, wherein a ratio of the first height to the channel height ranges from 1 to 1.2.

24. The semiconductor device of claim 21, wherein the second channel portion has a channel height above the first surface, wherein a ratio of the second height to the channel height ranges from 0.5 to 0.9.

25. The semiconductor device of claim 21, wherein the first channel portion and the second channel portion independently comprise germanium, gallium arsenide, silicon carbide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.

26. The semiconductor device of claim 21, wherein the first FET comprises a first gate stack on the first channel portion between the first S/D regions, and the second FET comprises a second gate stack on the second channel portion between the second S/D regions.