METHOD FOR MANUFACTURING A HYBRID INTEGRATED COMPONENT

• US 20130285165A1
• Filed: 04/18/2013
• Published: 10/31/2013
• Est. Priority Date: 04/25/2012
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: CLASSEN, Johannes, WEBER, Heribert
• Granted Patent: US 9,067,778 B2
• Time in Patent Office: Days
• US Class Current: 257/415
• CPC Class Codes: B81B 7/008 MEMS characterised by an electronic circuit specially adapted for controlling or driving the same B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: B81C 2203/0785 Transfer and j oin technology, i.e. forming the electronic processing unit and the micromechanical structure on separate substrates and joining the substrates
• CPC Class Codes: B81C 3/001 Bonding of two components
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]

Abstract

A manufacturing method for hybrid integrated components having a very high degree of miniaturization is provided, which hybrid integrated components each have at least two MEMS elements each having at least one assigned ASIC element. Two MEMS/ASIC wafer stacks are initially created independently of one another in that two ASIC substrates are processed independently of one another; a semiconductor substrate is mounted on the processed surface of each of the two ASIC substrates, and a micromechanical structure is subsequently created in each of the two semiconductor substrates. The two MEMS/ASIC wafer stacks are mounted on top of each other, MEMS on MEMS. Only subsequently are the components separated.

Claims

1. A method for manufacturing hybrid integrated components each having at least two MEMS elements, at least one ASIC element being assigned to each MEMS element, the method comprising:

initially creating two MEMS/ASIC wafer stacks independently of one another, by performing the following;

processing two ASIC substrates independently of one another;

mounting a semiconductor substrate on the processed surface of each of the two ASIC substrates; and

subsequently creating a micromechanical structure in each of the two semiconductor substrates;

mounting the two MEMS/ASIC wafer stacks on top of each other, MEMS on MEMS; and

subsequently separating the components.

2. The method as recited in claim 1, wherein the processed surface of at least one of the two ASIC substrates is structured by at least one of (i) creating at least one recess in an area beneath the micromechanical structure of the MEMS element to be created, and (ii) creating a pedestal structure for mounting an assigned MEMS substrate.

3. The method as recited in claim 2, wherein at least one of the two MEMS substrates is bonded to the assigned ASIC substrate.

4. The method as recited in claim 2, wherein at least one of the two MEMS substrates is thinned down to a predefined structural height of the micromechanical structure to be created, so that subsequently a micromechanical structure extending over the entire thickness of the MEMS substrate is created.

5. The method as recited in claim 2, wherein the micromechanical structure is created in at least one of the two MEMS substrates in a trench process.

6. The method as recited in claim 2, wherein at least one through-contact which establishes an electrical connection between a selected ASIC substrate and a surface of an MEMS substrate facing away from the selected ASIC substrate is created in at least one of the two MEMS substrates.

7. The method as recited in claim 6, wherein mechanical and electrical connections between the two MEMS/ASIC wafer stacks are established in a bond process.

8. A component, comprising:

at least two MEMS elements;

at least one ASIC element assigned to each of the at least two MEMS elements;

wherein micromechanical structures of the two MEMS elements each extend over the entire thickness of the MEMS element, and the two MEMS elements are mounted one on top of the other and sandwiched between the two ASIC elements so that the micromechanical structures of the two MEMS elements are capped by the two ASIC elements.

9. The component as recited in claim 8, wherein at least one through-contact for external contacting of the component is formed in at least one of the two ASIC elements.

10. The component as recited in claim 8, wherein at least one exposed terminal pad for external contacting of the component is formed on at least one of the ASIC elements.

11. The component as recited in claim 8, wherein:

the component is an inertial sensor component;

the micromechanical structure of at least one of the two MEMS elements includes at least one seismic mass and is equipped with a circuit for detecting deflections of the seismic mass;

the seismic mass extends at least over the entire thickness of the MEMS element; and

at least parts of an evaluation circuit for sensor signals are integrated on the assigned ASIC substrate.