FINFET DIODE WITH INCREASED JUNCTION AREA

• US 20130285208A1
• Filed: 04/26/2012
• Published: 10/31/2013
• Est. Priority Date: 04/26/2012
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Haran, Balasubramanian S., Ponoth, Shom, Yamashita, Tenko, Standaert, Theodorus Eduardus
• Granted Patent: US 8,592,263 B2
• Time in Patent Office: Days
• US Class Current: 257/546
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/6609 Diodes
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A FinFET diode and method of fabrication are disclosed. In one embodiment, the diode comprises, a semiconductor substrate, an insulator layer disposed on the semiconductor substrate, a first silicon layer disposed on the insulator layer, a plurality of fins formed in a diode portion of the first silicon layer. A region of the first silicon layer is disposed adjacent to each of the plurality of fins. A second silicon layer is disposed on the plurality of fins formed in the diode portion of the first silicon layer. A gate ring is disposed on the first silicon layer. The gate ring is arranged in a closed shape, and encloses a portion of the plurality of fins formed in the diode portion of the first silicon layer.

Claims

1. A method of forming a diode on a semiconductor structure, the structure comprised of a first silicon layer disposed on an insulator layer, the method comprising:

forming a plurality of diode fins on a diode portion of the semiconductor structure, wherein the plurality of fins terminate on the first silicon layer;

implanting dopants on the plurality of diode fins and first silicon layer;

forming a gate ring on the semiconductor structure;

forming a second silicon layer, disposed within the gate ring, and on the plurality of diode fins, and

doping the second silicon layer oppositely to the first silicon layer.

2. The method of claim 1, wherein implanting dopants on the plurality of diode fins and first silicon layer comprises implanting dopants selected from the group consisting of arsenic and phosphorous.

3. The method of claim 2, further comprising forming a plurality of fins in a non-diode portion of the semiconductor structure.

4. The method of claim 2, further comprising:

recessing a non-diode portion of the semiconductor structure, thereby forming a recessed portion and a non-recessed portion; and

forming a protective layer disposed on recessed portion and non-recessed portion of the semiconductor structure.

5. The method of claim 4, wherein forming a protective layer comprises depositing a nitride layer.

6. The method of claim 4, wherein forming a protective layer comprises forming a fin-top oxidation layer.

7. The method of claim 4, wherein recessing a non-diode portion of the semiconductor structure is performed by a reactive ion etch process.

8. The method of claim 2, wherein recessing a non-diode portion of the semiconductor structure is performed by:

forming a sacrificial oxidation layer on the non-diode portion of the semiconductor structure; and

removing the sacrificial oxidation layer with a wet etch process.

9. The method of claim 1, further comprising:

providing dopants in an outer region of the first silicon layer, wherein the dopant concentration in the outer region is greater than the dopant concentration in the diode portion of the first silicon layer.

10. The method of claim 9, wherein providing dopants in an outer region of the first silicon layer comprises forming an in situ phosphorous doped silicon epitaxial region disposed on the first silicon layer, outside of the gate ring.

11. The method of claim 1, wherein forming a second silicon layer, disposed within the gate ring, and on the plurality of fins in the diode portion, comprises forming an epitaxial in-situ P doped silicon layer.

12. A semiconductor structure comprising:

a semiconductor substrate;

an insulator layer disposed on the semiconductor substrate;

a first silicon layer disposed on the insulator layer;

a plurality of fins formed in a diode portion of the first silicon layer, wherein a region of the first silicon layer is disposed adjacent to each of the plurality of fins;

a second silicon layer disposed on the plurality of fins formed in the diode portion of the first silicon layer; and

a gate ring disposed on the first silicon layer, wherein the gate ring is arranged in a closed shape, and encloses a portion of the plurality of fins formed in the diode portion of the first silicon layer.

13. The semiconductor structure of claim 12, further comprising a plurality of fins in a non-diode portion of the first silicon layer, wherein the fins terminate on the insulator layer.

14. The semiconductor structure of claim 12, wherein the first silicon layer comprises a diode region disposed below the plurality of fins, and wherein the diode region is doped with an N type dopant at a first concentration range.

15. The semiconductor structure of claim 12, wherein the second silicon layer comprises an epitaxial P doped silicon layer.

16. The semiconductor structure of claim 15, wherein the second silicon layer contains boron and germanium.

17. The semiconductor structure of claim 14, wherein the first silicon layer comprises an outer region disposed outside of the gate ring, and wherein the diode region is doped with an N type dopant at a second concentration range, wherein the second concentration range is higher than the first concentration range.

18. A semiconductor structure comprising:

a first silicon layer;

a plurality of recesses formed in the first silicon layer, wherein the depth of each of the plurality of recesses is less than the depth of the first silicon layer, wherein an un-recessed area between each of the plurality of recesses forms a fin, thereby forming a plurality of fins;

a second silicon layer disposed on the first silicon layer, wherein contact surface area between the first silicon layer and second silicon layer is greater than the surface area of the plurality of fins; and

a gate ring disposed on the first silicon layer, wherein the gate ring is arranged in a closed shape, and encloses a portion of the plurality of fins.

19. The semiconductor structure of claim 18, wherein the second silicon layer comprises an epitaxial P doped silicon layer.

20. The semiconductor structure of claim 19, wherein the second silicon layer comprises BSiGe.