PROGRAMMABLE LSI

• US 20130285697A1
• Filed: 04/17/2013
• Published: 10/31/2013
• Est. Priority Date: 04/27/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki
• Granted Patent: US 9,654,107 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/17784 for supply voltage
• CPC Class Codes: H03K 19/17792 for operating speed

Abstract

An object is to achieve both suppression of operation delay and reduction in power consumption of a programmable LSI. A compiler generates, from source code, configuration data needed in a programmable LSI and a time schedule that shows a timing of using the data in the programmable LSI (a timing at which the data is held in a configuration memory) and a timing of storing the data in the programmable LSI before the data is used. Supply of new configuration data to the programmable LSI from the outside (storage of new configuration data) and data rewrite in the configuration memory in the programmable LSI (circuit reconfiguration) are performed independently and concurrently on the basis of the time schedule.

Claims

1. A semiconductor device comprising:

a programmable LSI comprising a logic circuit unit; and

a compiler configured to generate a time schedule and plural pieces of configuration data,

wherein the compiler is configured, independently and concurrently on the basis of the time schedule, to store the plural pieces of configuration data in the programmable LSI and reconfigure a configuration of the logic circuit unit in accordance with each of the plural pieces of configuration data.

2. The semiconductor device according to claim 1,

wherein the programmable LSI further comprises a bank group, and

wherein the bank group is configured to store the plural pieces of configuration data.

3. The semiconductor device according to claim 2,

wherein the bank group comprises a plurality of memory cells, and

wherein each of the memory cells comprises an input bit line, an output bit line, an input word line, an output word line, a reference potential line, a first transistor, a second transistor, and a third transistor.

4. The semiconductor device according to claim 3,

wherein the first transistor comprises a gate electrically connected to the input word line, and a source and a drain one of which is electrically connected to the input bit line,

wherein the second transistor comprises a gate electrically connected to the other of the source and the drain of the first transistor, and a source and a drain one of which is electrically connected to the reference potential line, and

wherein the third transistor comprises a gate electrically connected to the output word line, and a source and a drain one of which is electrically connected to the other of the source and the drain of the second transistor and the other of which is electrically connected to the output bit line.

5. The semiconductor device according to claim 3, further comprising a capacitor,

wherein the first transistor comprises a gate electrically connected to the input word line, and a source and a drain one of which is electrically connected to the input bit line,

wherein the second transistor comprises a gate electrically connected to the other of the source and the drain of the first transistor and one of a pair of electrodes of the capacitor, and a source and a drain one of which is electrically connected to the reference potential line, and

wherein the third transistor comprises a gate electrically connected to the output word line, and a source and a drain one of which is electrically connected to the other of the source and the drain of the second transistor and the other of which is electrically connected to the output bit line.

6. The semiconductor device according to claim 3,

wherein the first transistor comprises a gate electrically connected to the input word line, and a source and a drain one of which is electrically connected to the input bit line,

wherein the second transistor comprises a gate electrically connected to the output word line, and a source and a drain one of which is electrically connected to the reference potential line, and

wherein the third transistor comprises a gate electrically connected to the other of the source and the drain of the first transistor, and a source and a drain one of which is electrically connected to the other of the source and the drain of the second transistor and the other of which is electrically connected to the output bit line.

7. The semiconductor device according to claim 3, further comprising a capacitor,

wherein the first transistor comprises a gate electrically connected to the input word line, and a source and a drain one of which is electrically connected to the input bit line,

wherein the second transistor comprises a gate electrically connected to the output word line, and a source and a drain one of which is electrically connected to the reference potential line, and

wherein the third transistor comprises a gate electrically connected to the other of the source and the drain of the first transistor and one of a pair of electrodes of the capacitor, and a source and a drain one of which is electrically connected to the other of the source and the drain of the second transistor and the other of which is electrically connected to the output bit line.

8. The semiconductor device according to claim 3, wherein at least one of the first transistor, the second transistor, and the third transistor comprises an oxide semiconductor layer having a channel.

9. The semiconductor device according to claim 3, wherein each of the memory cells is configured to store multi-level data.

10. A semiconductor device comprising:

a programmable LSI comprising a logic circuit unit having a first configuration based on first configuration data, and a bank group comprising at least a first bank and a second bank, the first bank holding second configuration data and the second bank holding third configuration data; and

a compiler configured to generate a time schedule and plural pieces of configuration data,

wherein the compiler is configured, independently and concurrently on the basis of the time schedule, to store one of the plural pieces of configuration date in the first bank and reconfigure the first configuration to second configuration in accordance with the third configuration data.

11. The semiconductor device according to claim 10,

wherein the bank group comprises a plurality of memory cells, and

wherein each of the memory cells comprises an input bit line, an output bit line, an input word line, an output word line, a reference potential line, a first transistor, a second transistor, and a third transistor.

12. The semiconductor device according to claim 11,

wherein the first transistor comprises a gate electrically connected to the input word line, and a source and a drain one of which is electrically connected to the input bit line,

wherein the second transistor comprises a gate electrically connected to the other of the source and the drain of the first transistor, and a source and a drain one of which is electrically connected to the reference potential line, and

wherein the third transistor comprises a gate electrically connected to the output word line, and a source and a drain one of which is electrically connected to the other of the source and the drain of the second transistor and the other of which is electrically connected to the output bit line.

13. The semiconductor device according to claim 11, further comprising a capacitor,

wherein the first transistor comprises a gate electrically connected to the input word line, and a source and a drain one of which is electrically connected to the input bit line,

wherein the second transistor comprises a gate electrically connected to the other of the source and the drain of the first transistor and one of a pair of electrodes of the capacitor, and a source and a drain one of which is electrically connected to the reference potential line, and

wherein the third transistor comprises a gate electrically connected to the output word line, and a source and a drain one of which is electrically connected to the other of the source and the drain of the second transistor and the other of which is electrically connected to the output bit line.

14. The semiconductor device according to claim 11,

wherein the first transistor comprises a gate electrically connected to the input word line, and a source and a drain one of which is electrically connected to the input bit line,

wherein the second transistor comprises a gate electrically connected to the output word line, and a source and a drain one of which is electrically connected to the reference potential line, and

wherein the third transistor comprises a gate electrically connected to the other of the source and the drain of the first transistor, and a source and a drain one of which is electrically connected to the other of the source and the drain of the second transistor and the other of which is electrically connected to the output bit line.

15. The semiconductor device according to claim 11, further comprising a capacitor,

wherein the first transistor comprises a gate electrically connected to the input word line, and a source and a drain one of which is electrically connected to the input bit line,

wherein the second transistor comprises a gate electrically connected to the output word line, and a source and a drain one of which is electrically connected to the reference potential line, and

wherein the third transistor comprises a gate electrically connected to the other of the source and the drain of the first transistor and one of a pair of electrodes of the capacitor, and a source and a drain one of which is electrically connected to the other of the source and the drain of the second transistor and the other of which is electrically connected to the output bit line.

16. The semiconductor device according to claim 11, wherein at least one of the first transistor, the second transistor, and the third transistor comprises an oxide semiconductor layer having a channel.

17. The semiconductor device according to claim 11, wherein each of the memory cells is configured to store multi-level data.

18. A driving method for a semiconductor device comprising a compiler and a programmable LSI including a logic circuit unit, the method comprising the steps of:

generating a time schedule and plural pieces of configuration data; and

performing storage of the configuration data to the programmable LSI and reconfiguration of a configuration of the logic circuit unit in accordance with each of the plural pieces of configuration data independently and concurrently on the basis of the time schedule.

19. The driving method according to claim 18,

wherein the programmable LSI further comprises a bank group, and

wherein the bank group is configured to store the plural pieces of configuration data.

20. The driving method according to claim 19,

wherein the bank group comprises a plurality of memory cells, and

wherein each of the memory cells comprises an input bit line, an output bit line, an input word line, an output word line, a reference potential line, a first transistor, a second transistor, and a third transistor.

21. The driving method according to claim 20,

wherein the first transistor comprises a gate electrically connected to the input word line, and a source and a drain one of which is electrically connected to the input bit line,

wherein the second transistor comprises a gate electrically connected to the other of the source and the drain of the first transistor, and a source and a drain one of which is electrically connected to the reference potential line, and

wherein the third transistor comprises a gate electrically connected to the output word line, and a source and a drain one of which is electrically connected to the other of the source and the drain of the second transistor and the other of which is electrically connected to the output bit line.

22. The driving method according to claim 20,

wherein the semiconductor device further comprises a capacitor,

wherein the first transistor comprises a gate electrically connected to the input word line, and a source and a drain one of which is electrically connected to the input bit line,

wherein the second transistor comprises a gate electrically connected to the other of the source and the drain of the first transistor and one of a pair of electrodes of the capacitor, and a source and a drain one of which is electrically connected to the reference potential line, and

wherein the third transistor comprises a gate electrically connected to the output word line, and a source and a drain one of which is electrically connected to the other of the source and the drain of the second transistor and the other of which is electrically connected to the output bit line.

23. The driving method according to claim 20,

wherein the first transistor comprises a gate electrically connected to the input word line, and a source and a drain one of which is electrically connected to the input bit line,

wherein the second transistor comprises a gate electrically connected to the output word line, and a source and a drain one of which is electrically connected to the reference potential line, and

wherein the third transistor comprises a gate electrically connected to the other of the source and the drain of the first transistor, and a source and a drain one of which is electrically connected to the other of the source and the drain of the second transistor and the other of which is electrically connected to the output bit line.

24. The driving method according to claim 20,

wherein the semiconductor device further comprises a capacitor,

wherein the first transistor comprises a gate electrically connected to the input word line, and a source and a drain one of which is electrically connected to the input bit line,

wherein the second transistor comprises a gate electrically connected to the output word line, and a source and a drain one of which is electrically connected to the reference potential line, and

wherein the third transistor comprises a gate electrically connected to the other of the source and the drain of the first transistor and one of a pair of electrodes of the capacitor, and a source and a drain one of which is electrically connected to the other of the source and the drain of the second transistor and the other of which is electrically connected to the output bit line.

25. The driving method according to claim 19, wherein at least one of the first transistor, the second transistor, and the third transistor comprises an oxide semiconductor layer having a channel.

26. The driving method according to claim 19, wherein each of the memory cells is configured to store multi-level data.