RE-PROGRAMMABLE ANTIFUSE FPGA UTILIZING RESISTIVE CeRAM ELEMENTS

• US 20130285699A1
• Filed: 04/26/2013
• Published: 10/31/2013
• Est. Priority Date: 04/26/2012
• Status: Active Grant

• Current Assignee: Symetrix Memory, LLC
• Original Assignee: Symetrix Corporation
• Inventors: Paz de Araujo, Carlos A., Celinska, Jolanta, McWilliams, Christopher Randolph
• Granted Patent: US 8,816,719 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

A re-programmable antifuse field programmable gate array (FPGA) integrated circuit, the FPGA comprising: a plurality of CeRAM resistive switching elements forming a connection block, the switching elements capable of being switched from a conductive (ON) state to a non-conductive (OFF) state and back to a conductive (ON) state; a plurality of logic elements forming a logic block; and a programming circuit for turning the CeRAM switching elements OFF and ON to connect the logic elements to form the FPGA.

Claims

1. A re-programmable antifuse field programmable gate array (FPGA) integrated circuit, said FPGA comprising:

a power source;

a plurality of CeRAM resistive switching elements forming a connection block, said switching elements capable of being switched from a conductive (ON) state to a non-conductive (OFF) state and back to a conductive (ON) state;

a plurality of logic elements forming a logic block;

a plurality of transistors forming a switching block;

said transistors connected between said power source and said CeRAM resistive elements;

a control circuit for applying control pulses to said transistors; and

a microprocessor connected to said control circuit for turning said CeRAM switching elements OFF and ON to connect said logic elements to form said FPGA.

2. An FPGA as in claim 1 wherein said connection block is formed in one or more wiring layers above said logic block.

3. An FPGA as in claim 1 wherein said transistors are current-limited transistors.

4. An FPGA as in claim 1 wherein said logic block is a CMOS logic block.

5. An FPGA as in claim 4, and further including CMOS memory elements in said CMOS logic block.

6. An FPGA as in claim 2, and further including a plurality of metal/insulator/metal (MIM) memory elements in said layer including said CeRAM switching elements.

7. An FPGA as in claim 1 wherein said switching block is formed in the same layer or layers as said connection block.

8. An FPGA as in claim 1 wherein said CeRAM switching elements comprise nickel oxide (NiO) or other transition metal oxide.

9. An FPGA as in claim 1 wherein said CeRAM resistive switching elements are capable of being switched 10¹⁰ times with less than 25% change in the resistance of the ON state and the OFF state.

10. An FPGA as in claim 1 wherein said CeRAM resistive switching elements are capable of being switched 10¹⁰ times with less than 10% change in the resistance of the ON state and the OFF state.

11. An FPGA as in claim 1 wherein said CeRAM resistive switching elements are formed in a crossbar architecture.

12. A method of forming a first Field Programmable Gate Array (FPGA), said method comprising:

providing a plurality of CeRAM resistive switching elements, said switching elements capable of being switched from a conductive state to a non-conductive state and back to a conductive state; and

a plurality of logic elements; and

programming said CeRAM switching elements to be ON or OFF to connect one or more of said logic elements to form said FPGA.

13. A method as in claim 12 wherein said programming comprises applying a voltage to one or more of said CeRAM switching elements while limiting the current applied to said switching elements.

14. A method as in claim 13 wherein said current is 5 milliamps (mA) or less.

15. A method as in claim 13 wherein said current is 2 mA or less.

16. A method as in claim 13 wherein said voltage is 2 volts or less.

17. A method as in claim 13 wherein said limiting the current comprises applying said voltage through a current-limited transistor.

18. A method as in claim 17 wherein said limiting the current comprises saturating said transistor.

19. A method as in claim 12, and further comprising reprogramming said CeRAM switching elements to form a second FPGA different than said first FPGA.

20. A method as in claim 12, and further comprising operating said FPGA with a voltage signal of two volts or less.

21. A method as in claim 12, and further comprising operating said FPGA with a voltage signal of 1 volt or less.

22. A method as in claim 12, and further comprising operating said FPGA with a current of one-half volt or less.

23. A re-programmable antifuse field programmable gate array (FPGA) integrated circuit, said FPGA comprising:

a plurality of CeRAM resistive switching elements forming a connection block, said switching elements capable of being switched from a conductive (ON) state to a non-conductive (OFF) state and back to a conductive (ON) state;

a plurality of logic elements forming a logic block; and

a programming circuit for turning said CeRAM switching elements OFF and ON to connect said logic elements to form said FPGA.

24. An FPGA as in claim 23 wherein said CeRAM switching elements comprise nickel oxide (NiO).

25. An FPGA as in claim 23 wherein said CeRAM resistive switching elements are capable of being switched 10¹⁰ times with less than 25% change in the resistance of the ON state and the OFF state.

26. An FPGA as in claim 23 wherein said CeRAM resistive switching elements are capable of being switched 10¹⁰ times with less than 10% change in the resistance of the ON state and the OFF state.

27. An FPGA as in claim 23 wherein said CeRAM resistive switching elements are formed in a crossbar architecture.

28. An FPGA as in claim 23 wherein said FPGA is capable of being operated with a voltage of 2 volts or less.