MULTIPLE CHANNEL PHASE DETECTION

• US 20130285720A1
• Filed: 04/26/2012
• Published: 10/31/2013
• Est. Priority Date: 04/26/2012
• Status: Abandoned Application

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Jibry, Rafel
• Application Number:
  US13/456,574
• Publication Number:
  US 20130285720A1
• Time in Patent Office: Days
• US Class Current: 327/156
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop

Abstract

A signal processing device to utilize multiple channel phase detection includes a first phase detector for a first Phase Locked Loop (PLL) of a first channel, the first phase detector to generate phase error information from an input of the first channel. The device also includes a second phase detector of a second PLL of a second channel, the second phase detector to generate phase error information from an input of the second channel. Both the first PLL and the second PLL are to receive phase error information from both the first phase detector and the second phase detector.

Claims

1. A signal processing device to utilize multiple channel phase detection, the device comprising:

a first phase detector for a first Phase Locked Loop (PLL) of a first channel, said first phase detector to generate phase error information from an input of said first channel; and

a second phase detector of a second PLL of a second channel, said second phase detector to generate phase error information from an input of said second channel;

wherein, both said first PLL and said second PLL are to receive phase error information from both said first phase detector and said second phase detector.

2. The device of claim 1, wherein said first PLL is to collate information from said first phase detector and said second phase detector.

3. The device of claim 1, further comprising, a global collating element to collate phase information from both said first phase detector and said second phase detector to produce collated phase information for said first PLL and said second PLL.

4. The device of claim 1, wherein said first phase detector comprises a higher order phase detector.

5. The device of claim 4, wherein said higher order phase detector comprises an Extended Partial Response 4 (EPR4) phase detector.

6. The device of claim 1, wherein said first phase detector provides information for an integral path of said first PLL.

7. The device of claim 1, further comprising a lower order phase detector for said first channel, said lower order phase detector to provide phase information to a proportional path of said first PLL.

8. A method for utilizing multiple channel phase detection, the method comprising:

with a first Phase Locked Loop (PLL) of a first channel, receiving phase error information for said first channel from a first phase detector and phase error information for a second channel from a second phase detector; and

with a second PLL of said second channel, receiving phase error information from said second phase detector and said first phase detector.

9. The method of claim 8, further comprising, with said first PLL, collating phase information from both said first phase detector and said second phase detector.

10. The method of claim 8, further comprising, with a global collating element, collating phase information from both said first phase detector and said second phase detector.

11. The method of claim 10, further comprising, with said global collating element, sending collated phase information to both said first PLL and said second PLL.

12. The method of claim 8, wherein said first phase detector comprises a higher order phase detector.

13. The method of claim 8, wherein said first phase detector provides information for an integral path of said first PLL.

14. The method of claim 8, further comprising, with a lower order phase detector for said first channel, providing phase information to a proportional path of said first PLL.

15. A multiple channel phase detection system comprising:

a number of channels that are nominally operating at a same frequency, each channel comprising;

a phase detector; and

a Phase Locked Loop (PLL);

wherein each PLL for each of said channels is to receive phase error information for its respective channel and phase error information from at least one phase detector of a separate channel.