PHASE LOCKED LOOP WITH A FREQUENCY MULTIPLIER AND METHOD OF CONFIGURING THE PHASE LOCKED LOOP

• US 20130285722A1
• Filed: 08/08/2012
• Published: 10/31/2013
• Est. Priority Date: 04/30/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHOU, Mao-Hsuan
• Granted Patent: US 9,503,103 B2
• Time in Patent Office: Days
• US Class Current: 327/157
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

A phase locked loop (PLL) circuit includes a frequency multiplier and a fractional-N type PLL. The clock output of the frequency multiplier is electrically connected to the clock input of the fractional-N type PLL. The loop bandwidth of the frequency multiplier of the PLL is smaller than the loop bandwidth of the fractional-N type PLL of the PLL.

Claims

1. A phase locked loop (PLL) circuit, comprising:

a frequency multiplier comprising a first clock input and a first clock output; and

a fractional-N type PLL comprising a second clock input and a second clock output, wherein

the first clock output of the frequency multiplier is electrically connected to the second clock input of the fractional-N type PLL; and

a loop bandwidth of the frequency multiplier is less than a loop bandwidth of the fractional-N type PLL.

2. The phase locked loop (PLL) circuit of claim 1, wherein the frequency multiplier further comprises an integer-N type PLL that comprises a clock input and a clock output, and the clock input of the integer-N type PLL is electrically connected to the first clock input, and the clock output of the integer-N type PLL is electrically connected to the first clock output

3. The phase locked loop (PLL) circuit of claim 1, wherein at least one of the frequency multiplier and the fractional-N type PLL includes configurable options that are arranged to adjust the loop bandwidth of the at least one of the frequency multiplier and the fractional-N type PLL.

4. The phase locked loop (PLL) circuit of claim 3, wherein each of the at least one of the frequency multiplier and the fractional-N type PLL further comprises a charge pump, a voltage controlled oscillator (VCO) and a loop filter;

and wherein the configurable options are arranged to adjust electrical characteristics of at least one of the charge pump, the VCO and the loop filter.

5. The phase locked loop (PLL) circuit of claim 3, wherein the configurable options include configurable pins;

and logic values for the configurable pins are pre-determined.

6. The phase locked loop (PLL) circuit of claim 1, wherein the fractional-N type PLL further comprises a phase and frequency detector (PFD) and a charge pump (CP), and an output clock frequency of the frequency multiplier is less than an operating frequency of the PFD and of the CP of the fractional-N type PLL.

7. A phase locked loop (PLL) circuit, comprising:

a first fractional-N type PLL comprising a first clock input and a first clock output;

a second fractional-N type PLL comprising a second clock input and a second clock output; and

a frequency multiplier comprising a third clock input and a third clock output;

wherein

the third clock output of the frequency multiplier is electrically connected to the first clock input of the first fractional-N type PLL to form a first PLL;

the third clock output of the frequency multiplier is electrically connected to the second clock input of the second fractional-N type PLL to form a second PLL;

a fourth clock output of the first PLL is electrically connected to the first clock output of the first fractional-N type PLL;

a fifth clock output of the second PLL is electrically connected to the second clock output of the second fractional-N type PLL; and

a loop bandwidth of the frequency multiplier is less than a loop bandwidth of each of the fractional-N type PLLs in the first and second PLL.

8. The phase locked loop (PLL) circuit of claim 7, wherein the frequency multiplier further comprises an integer-N type PLL that comprises a clock input and a clock output, and the clock input of the integer-N type PLL is electrically connected to the third clock input, and the clock output of the integer-N type PLL is electrically connected to the third clock output.

9. The phase locked loop (PLL) circuit of claim 7, wherein at least one of the frequency multiplier and the first and second fractional-N type PLLs includes configurable options that are arranged to determine the loop bandwidth of the at least one of the frequency multiplier and the first and second fractional-N type PLLs.

10. The phase locked loop (PLL) circuit of claim 9, wherein the at least one of the frequency multiplier and the first and second fractional-N type PLL further comprises a charge pump, a voltage controlled oscillator (VCO) and a loop filter;

and wherein the configurable options are arranged to adjust at least one of the charge pump, the VCO and the loop filter in the at least one of the frequency multiplier and the first and second fractional-N type PLL.

11. The phase locked loop (PLL) circuit of claim 9, wherein the configurable options further comprise configurable pins;

and logic values for the configurable pins are pre-determined.

12. The phase locked loop (PLL) circuit of claim 11, wherein the configurable pins are electrically connected to data outputs of non-volatile memories.

13. The phase locked loop (PLL) circuit of claim 7, wherein the fourth clock output is electrically connected to a first group of circuits, and the fifth clock output is electrically connected to a second group of circuits.

14. The phase locked loop (PLL) circuit of claim 7, wherein the fourth clock output and the fifth clock output are electrically connected to a first group of circuits.

15. A method of configuring a phase locked loop (PLL), comprising:

calculating a feedback path divider ratio of a first stage circuit of the PLL;

calculating a feedback path divider ratio of a second stage circuit of the PLL;

determining at least one of a charge pump current, a voltage controlled oscillator (VCO) gain and a loop filter capacitance of the first stage circuit and of the second stage circuit of the PLL such that a bandwidth ratio of the PLL is less than 1; and

adjusting configurable options of the at least one of charge pump current, the VCO gain and loop filter of the first stage circuit and the second stage circuit of the PLL such that a bandwidth ratio of the PLL continues to be less than 1.

16. The method of claim 15, wherein the first stage circuit of the phase locked loop (PLL) comprises an integer-N type PLL, and a clock input of the integer-N type PLL is electrically connected to a clock input of the first stage circuit of the PLL, and a clock output of the integer-N type PLL is electrically connected to a clock output of the first stage circuit of the PLL.

17. The method of claim 15, wherein the second stage circuit further comprises a phase and frequency detector (PFD) and a charge pump (CP), and an output clock frequency of the first stage circuits is less than an operating frequency of the PFD and the CP of the second stage circuit.

18. The method of claim 15, wherein the second stage circuit of the phase locked loop (PLL) comprises a fractional-N type PLL, and a clock input of the fractional-N type PLL is electrically connected to a clock input of the second stage circuit of the PLL, and a clock output of the fractional-N type PLL is electrically connected to a clock output of the second stage circuit of the PLL.

19. The method of claim 15, wherein the configurable options include configurable pins;

and logic values of the configurable pins are pre-determined.

20. The method of claim 19, wherein the configurable pins are connected to data outputs of non-volatile memories.