Methods, apparatus and system to support large-scale micro- systems including embedded and distributed power supply, thermal regulation, multi-distributedsensors and electrical signal propagation

• US 20130285739A1
• Filed: 03/01/2013
• Published: 10/31/2013
• Est. Priority Date: 09/07/2010
• Status: Abandoned Application

• Current Assignee: Polyvalor LP, Transfert Plus, Société en Commandite , Valuqo Societe En Commandite
• Original Assignee: Corporation De L'Ecole Polytechnique De Montreal, Université du Québec à Montréal
• Inventors: Savaria, Yvon, Blaquire, Yves, Basile-Bellavance, Yan, Valorge, Olivier, Lahkssassi, Ahmed, Andr, Walder, Laflamme Mayer, Nicolas, Bougataya, Mohamed, Sawan, Mohamad
• Application Number:
  US13/782,868
• Publication Number:
  US 20130285739A1
• Time in Patent Office: Days
• US Class Current: 327/565
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/345 Arrangements for heating thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/00 Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19107 off-chip wires
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

The present invention relates to technologies for integrated circuits and Large Area Integrated Circuits (LAICs), which are integrated circuits made from photo-repetition of one or several reticle image fields, stitched together on at least one lithographic process layer. It also relates to a specific class of LAIC that can connect to the contacts of other ICs placed on its surface, where specific contact detection algorithms means are disclosed. The innovations include means for defect tolerance of serial communication links, means for efficient diagnosis of short and stuck-at faults in regular reconfigurable network, means for a programmable interposer for rapid prototyping of 3D stacked chips, means to build efficient large area micro-system devices (LAMS), with distributed and configurable hierarchical structures for power supply, thermal regulation and signal propagation, means to reduce mechanical/thermal/thermo-mechanical issues in LAMS devices, means to propagate analog signal on a configurable digital network, means to predict thermo-mechanical stress peaks.

Claims

1. An integrated circuit system interconnect device having an integrated circuit substrate comprising:

surface contacts for making direct contact with contacts of a plurality of integrated circuit components to interconnect said components to form said system;

wherein said substrate comprises support circuitry serving said components, said support circuitry comprising at least one of;

one or more voltage regulators provided within said substrate for receiving source power and delivering a voltage level to at least one of said surface contacts for delivering power to ones of said contacts of said plurality of integrated circuit components;

an array of heat transfer blocks distributed over and coupled to one surface of said substrate to draw heat from said substrate while allowing said substrate to expand and contract due to temperature variations during operation and storage without compromising mechanical and electrical integrity of said system, wherein another surface of said substrate comprises said surface contacts for interconnecting said plurality of components;

a distributed differential signal pair switch matrix permitting a selected one of said surface contacts to be paired with a selected one of a plurality of other ones of said surface contacts to support differential signaling;

distributed signal measurement circuitry for determining one or more of;

power drawn;

voltage level drops;

current levels drawn; and

signal integrity at at least some of said surface contacts;

one or more clock or reset trees;

analog circuitry for supporting substantially analog functions;

analog-to-digital (ADC) or digital-to-analog (DAC) circuits;

one or more trimmable analog components;

test circuitry to perform testing of circuitry;

at least one controller and circuitry permitting the controller to perform configuring of circuitry through said surface contacts; and

thermal and/or mechanical stress sensors distributed within said substrate.

2. The system as claimed in claim 1, wherein said voltage regulators comprise a number of voltage regulators distributed within said substrate for delivering regulated voltage where needed to said surface contacts.

3. The system as claimed in claim 2, wherein said voltage regulators are programmable, further comprising one or more power feed conductive paths for transporting external power, wherein said surface contacts are provided on a first surface of said substrate, said power feed conductive paths comprise contacts distributed over a second surface of said substrate that connect to said substrate to deliver power to said programmable voltage regulators.

4. The system as claimed in claim 3, further comprising passive devices mounted to said second surface in proximity to said contacts distributed over said second surface of said substrate.

5. The system as claimed in claim 4, wherein said passive devices are included in one or more power supply blocks connected to said contacts distributed over said second surface of said substrate and said power supply blocks having:

one or more power signal inputs; and

one or more configurable power regulator units working with said passive devices to deliver a desired power profile to said second surface contacts.

6. The system as claimed in claim 4, wherein said power supply blocks are integrated into said array of heat transfer blocks.

7. The system as claimed in claim 1, comprising said voltage regulators and said signal measurement circuitry, wherein said signal measurement circuitry is integrated with said voltage regulators.

8. The system as claimed in claim 1, comprising said heat transfer blocks, wherein said heat transfer blocks are provided in a rectangular array with spacing between said blocks.

9. The system as claimed in claim 1, comprising said heat transfer blocks, wherein said heat transfer blocks encapsulate power supply circuit components.

10. The system as claimed in claim 1, comprising said test circuitry, said test circuitry comprising one or more of test controllers, and a fault-tolerant cell architecture comprising cells distributed over said substrate, wherein said cells each comprise at least one of said test controllers.

11. The system as claimed in claim 10, wherein said test controllers are configured to have a field-programmable variable length scan chain path.

12. The system as claimed in claim 1, wherein said test circuitry comprises one or more test controllers.

13. The system as claimed in claim 12, wherein said test controllers are configured to perform substantially at the same time more than one test.

14. The system as claimed in claim 1, wherein said test circuitry comprises one or more self-test circuitry.

15. The system as claimed in claim 14, wherein said self-test circuitry is configured to perform a built-in self test of circuitry within said substrate.

16. The system as claimed in claim 14, wherein said self-test circuitry is configured to perform a built-in self test of circuitry external to said substrate and connected to said surface contacts.

17. The system as claimed in claim 1, comprising said test circuitry, wherein said test circuitry comprises a hardware assertion module.

18. The system as claimed in claim 1, comprising said thermal and/or mechanical stress sensors, further comprising a transient thermo-mechanical peak stress monitoring and prediction unit.

19. The system as claimed in claim 1, comprising said thermal and/or mechanical stress sensors, wherein said sensors comprise stress sensors, further comprising:

a pressure applicator for pressing components onto said first surface of said substrate; and

a stress analyzer connected to said stress sensors for determining if pressure applied to said components is uneven and/or at risk of causing damage to said components and/or said substrate.

20. The system as claimed in claim 1, comprising said distributed signal measurement circuitry.

21. The system as claimed in claim 20, wherein said signal measurement circuitry is integrated with said test circuitry.

22. The system as claimed in claim 20, wherein said signal measurement circuitry measures signal integrity.

23. The system as claimed in claim 20, wherein said signal measurement circuitry measures power drawn by said components.

24. The system as claimed in claim 1, comprising said distributed differential signal pair switch matrix.

25. The system as claimed in claim 24, comprising a differential amplifier selectably connectable to said differential pairs.

26. The system as claimed in claim 1, wherein said system is programmable, said system comprising:

at least one interconnect switch matrix for interconnecting said surface contacts as programmed for analog and/or digital signal transmission; and

a power supply comprising one or more power feed conductive paths for transporting external power.

27. The system as claimed in claim 1, wherein said substrate is singulated from a wafer and corresponds to an area of a single integrated circuit fabrication image field.

28. The system as claimed in claim 1, wherein said substrate is a large-area integrated circuit.

29. The system as claimed in claim 28, further comprising a pressure applicator for pressing components onto said surface contacts of said substrate.

30. The system as claimed in claim 1, wherein said surface contacts comprise alignment-insensitive contacts.

31. The system as claimed in claim 1, further comprising a compliant Z-axis film for improving electrical contact between said surface contacts and corresponding contacts of said integrated circuit component.

32. The system as claimed in claim 1, comprising said clock or reset trees.

33. The system as claimed in claim 32, further comprising fault tolerant interconnect circuitry between at least some of said clock or reset trees.

34. The system as claimed in claim 26, comprising one or more said ADC, wherein a digital output of said ADC is propagated through the interconnect switch matrix.

35. The system as claimed in claim 26, comprising one or more said DAC, wherein signals propagated through said interconnect switch matrix are converted to analog through said DAC.

36. The system as claimed in claim 1, comprising said trimmable analog components.

37. The system as claimed in claim 1, wherein said substrate is an interposer placed between integrated circuit components, said surface contacts being provided on a top surface and a bottom surface of said substrate.

38. The system as claimed in claim 37, wherein two or more of said substrates are provided in said system for stacking three or more integrated circuit components.

39. The system as claimed in claim 38, wherein two or more of said substrates are provided in said system with said substrates partly overlapping and stacked to allow said system to be layered and to spread out laterally, said substrates making direct contact between themselves.

40. The system as claimed in claim 37, wherein power supply is wire bonded to said substrate.

41. The system as claimed in claim 37, wherein test output data are communicated from said substrate without passing through said integrated circuit components.

42. The system as claimed in claim 37, wherein said system is packaged as a single component.

43. A method of manufacturing an integrated circuit system comprising a plurality of integrated circuit components, the method comprising:

using circuit design software tool and a programmable system as claimed in claim 26 to prototype said integrated circuit system and to generate a printed circuit board design for said components;

providing a printed circuit board according to said design;

assembling said integrated circuit system using said printed circuit board and said components.

44. A method of manufacturing an integrated circuit system comprising a plurality of integrated circuit components, the method comprising:

using circuit design software tool and a programmable system as claimed in claim 37, wherein said interposer is programmable, to prototype said integrated circuit system and to generate a non-programmable interposer design for said components;

providing a non-programmable interposer according to said design;

assembling said integrated circuit system using said non-programmable interposer and said components.

45. An integrated circuit substrate comprising:

surface contacts for making contacts with a plurality of integrated circuit components;

wherein some surface contacts receive and process external data from said surface contacts and drive some other surface contacts with processing results;

wherein said substrate comprises support circuitry serving said components, said support circuitry comprising at least one of;

one or more voltage regulators provided within said substrate for receiving source power and delivering a voltage level to at least one of said surface contacts for delivering power to ones of said contacts of said plurality of integrated circuit components;

a distributed differential signal pair switch matrix permitting a selected one of said surface contacts to be paired with a selected one of a plurality of other ones of said surface contacts to support differential signaling;

distributed signal measurement circuitry for determining one or more of;

power drawn;

voltage level drops;

current levels drawn; and

signal integrity at at least some of said surface contacts;

analog circuitry for supporting substantially analog functions;

analog-to-digital (ADC) or digital-to-analog (DAC) circuits;

test circuitry to perform testing of circuitry;

at least one controller and circuitry permitting the controller to perform configuring of circuitry.

46. The system as claimed in claim 45, wherein said voltage regulators comprise a number of voltage regulators distributed within said substrate for delivering regulated voltage where needed to said surface contacts.

47. The system as claimed in claim 46, wherein said voltage regulators are programmable, further comprising one or more power feed conductive paths for transporting external power up to these voltage regulators.

48. The system as claimed in claim 45, comprising said voltage regulators and said signal measurement circuitry, wherein said signal measurement circuitry is integrated with said voltage regulators.

49. The system as claimed in claim 45, comprising said test circuitry, wherein said test circuitry comprises a hardware assertion module.

50. The system as claimed in claim 45, comprising said distributed signal measurement circuitry.

51. The system as claimed in claim 50, wherein said signal measurement circuitry is integrated with said test circuitry.

52. The system as claimed in claim 50, wherein said signal measurement circuitry measures signal integrity.

53. The system as claimed in claim 50, wherein said signal measurement circuitry measures power drawn by said components.

54. The system as claimed in claim 45, comprising said distributed differential signal pair switch matrix.

55. The system as claimed in claim 54, comprising a differential amplifier selectably connectable to said differential pairs.

56. The system as claimed in claim 45, wherein said system is programmable, said system comprising:

at least one interconnect switch matrix for interconnecting said surface contacts as programmed for analog and/or digital signal transmission; and

a power supply comprising one or more power feed conductive paths for transporting external power.

57. The system as claimed in claim 45 comprising one or more said ADC, wherein a digital output of said ADC is propagated through the interconnect switch matrix.

58. The system as claimed in claim 45, comprising one or more said DAC, wherein signals propagated through said interconnect switch matrix are converted to analog through said DAC.