Reconfigurable Graphics Processor for Performance Improvement

• US 20130286026A1
• Filed: 11/21/2011
• Published: 10/31/2013
• Est. Priority Date: 11/21/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kaburlasos, Nikos, Samson, Eric C.
• Granted Patent: US 10,242,418 B2
• Time in Patent Office: Days
• US Class Current: 345/501
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G09G 2360/08 Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs
• CPC Class Codes: G09G 5/36 characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Power gating a portion of a graphics processor may be used to improve performance or to achieve a power budget. A processor granularity, such as a slice or subslice, may be gated.

Claims

1. A method comprising:

power gating a portion less than the entirety of a graphics processor.

2. The method of claim 1 including power gating a slice.

3. The method of claim 1 including power gating a subslice.

4. The method of claim 1 including changing operating frequency after power gating.

5. The method of claim 1 including power gating the portion off only after all pending tasks on the portion have completed.

6. The method of claim 1 including power gating for power budgeting.

7. The method of claim 1 including determining if performance was improved by power gating.

8. The method of claim 1 including checking power budget after power gating.

9. The method of claim 7 including determining target switching capacitance and target application ratio.

10. The method of claim 9 including using one of silicon measurements or energy monitor counters.

11. A non-transitory computer readable medium storing instructions for execution by a computer to:

power gate only one of at least two portions of a graphics processor.

12. The medium of claim 11 further storing instructions to power gate a slice.

13. The medium of claim 11 further storing instructions to power gate a subslice.

14. The medium of claim 11 further storing instructions to change operating frequency after power gating.

15. The medium of claim 11 further storing instructions to power gate the portion off only after all pending tasks on the portion have completed.

16. The medium of claim 11 further storing instructions to power gate for power budgeting.

17. The medium of claim 11 further storing instructions to determine if performance was improved by power gating.

18. The medium of claim 11 further storing instructions to check power budget after power gating.

19. The medium of claim 17 further storing instructions to determine target switching capacitance and target application ratio.

20. The medium of claim 19 further storing instructions to use one of silicon measurements or energy monitor counters.

21. A graphics processor comprising:

first and second independently gateable portions of the graphics processor; and

logic to power gate a first portion and not the second portion of the graphics processor.

22. The graphics processor of claim 21, said logic to power gate a slice.

23. The graphics processor of claim 21, said logic to power gate a subslice.

24. The graphics processor of claim 21, said logic to change operating frequency after power gating.

25. The graphics processor of claim 21, said logic to power gate the portion off only after all pending tasks on the portion have completed.

26. The graphics processor of claim 21, said logic to power gate for power budgeting.

27. The graphics processor of claim 21, said logic to determine if performance was improved by power gating.

28. The graphics processor of claim 21, said logic to check power budget after power gating.

29. The graphics processor of claim 27, said logic to determine target switching capacitance and target application ratio.

30. The graphics processor of claim 29, said logic to use one of silicon measurements or energy monitor counters.