LOW POWER CONTENT ADDRESSABLE MEMORY HITLINE PRECHARGE AND SENSING CIRCUIT

• US 20130286705A1
• Filed: 04/26/2012
• Published: 10/31/2013
• Est. Priority Date: 04/26/2012
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Grover, David B., Stephani, Richard J., Browning, Christopher D.
• Application Number:
  US13/456,419
• Publication Number:
  US 20130286705A1
• Time in Patent Office: Days
• US Class Current: 365/49.17
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

An apparatus and a method of operating the apparatus. The apparatus includes a driver circuit and a memory circuit. The driver circuit may be configured to precharge a hitline in response to a predetermined voltage level and a control signal and sense a result of a compare operation based upon a hitline signal on the hitline. The driver circuit generally precharges the hitline to a voltage level lower than the predetermined voltage level and senses the result of the compare operation using the full predetermined voltage level. The memory circuit may be configured to perform the compare operation using the hitline.

Claims

1. An apparatus comprising:

a driver circuit configured to precharge a hitline in response to a predetermined voltage level and a control signal and sense a result of a compare operation based upon a hitline signal on said hitline, wherein said driver circuit precharges said hitline to a voltage level lower than said predetermined voltage level and senses said result of said compare operation using the full predetermined voltage level; and

a memory circuit configured to perform said compare operation using said hitline.

2. The apparatus according to claim 1, wherein said predetermined voltage level is selected from a supply voltage and a voltage level lower than said supply voltage.

3. The apparatus according to claim 1, wherein said memory circuit is configured as a content addressable memory (CAM) configured to operate in (i) a compare mode and (ii) a read/write mode.

4. The apparatus according to claim 1, wherein said driver circuit is coupled to said hitline by a device having a first threshold voltage when said driver circuit is precharging said hitline and a second threshold voltage when said driver circuit is sensing said hitline signal.

5. The apparatus according to claim 4, wherein said device comprises a pass gate having said first threshold voltage when a control input is in a first state and said second threshold voltage when said control input is in a second state.

6. The apparatus according to claim 5, wherein said pass gate comprises a first transistor having a first transistor threshold voltage and a second transistor having a second transistor threshold voltage, conduction paths of said first and said second transistors are connected in parallel, and said first transistor threshold voltage is lower than said second transistor threshold voltage.

7. The apparatus according to claim 1, wherein said driver circuit reduces overall dynamic power consumption of said memory during compare operations.

8. The apparatus according to claim 1, wherein said driver circuit is configured to precharge a sensing node to said predetermined voltage level and said hitline to approximately one-half of said predetermined voltage level.

9. The apparatus according to claim 1, wherein said driver circuit comprises a hitline precharge and sensing circuit.

10. The apparatus according to claim 9, wherein said apparatus comprises a plurality of said hitline precharge and sensing circuits.

11. The apparatus according to claim 10, wherein said plurality of hitline precharge and sensing circuits are selectively activated.

12. The apparatus according to claim 1, further comprising:

a control circuit configured to generate said control signal.

13. The apparatus according to claim 1, wherein said apparatus is implemented as one or more integrated circuits.

14. The apparatus according to claim 1, wherein said hitline comprises at least one of a local hitline and a global hitline.

15. An apparatus comprising:

means for precharging a hitline in response to a predetermined voltage level and a control signal and sensing a result of a compare operation based upon a hitline signal on said hitline, wherein said precharging and sensing means precharges said hitline to a voltage level lower than said predetermined voltage level and senses said result of said compare operation using the full predetermined voltage level; and

a memory circuit configured to perform said compare operation using said hitline.

16. A method for reducing power in a memory, comprising the steps of:

precharging a hitline in response to a predetermined voltage level and a control signal, wherein said hitline is precharged to a voltage level lower than said predetermined voltage level;

performing a compare operation using said hitline; and

sensing a result of said compare operation based upon a hitline signal on said hitline, wherein said result of said compare operation is sensed using the full predetermined voltage level.

17. The method according to claim 16, wherein said hitline is precharged through a device having a first threshold voltage when a control input is in a first state and a second threshold voltage when said control input is in a second state.

18. The method according to claim 17, wherein said device comprises a pass gate having said first threshold voltage when a control input is in said first state and said second threshold voltage when said control input is in said second state.

19. The method according to claim 18, wherein said pass gate comprises a first transistor having a first transistor threshold voltage and a second transistor having a second transistor threshold voltage, conduction paths of said first and said second transistors are connected in parallel, and said first transistor threshold voltage is lower than said second transistor threshold voltage.

20. The method according to claim 19, further comprising one or more of (i) selecting said first transistor from a lower voltage threshold cell library and said second transistor from a higher voltage threshold cell library, (ii) implementing said first transistor having a first length and said second transistor having a second length that is different from said first length, and (iii) implementing said first and said second transistors with different bulk voltages.