VERTICAL STRUCTURE SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

• US 20130286735A1
• Filed: 06/18/2013
• Published: 10/31/2013
• Est. Priority Date: 06/07/2010
• Status: Active Grant

• Current Assignee: Hansoo Kim, Sung-Min Hwang, Sun-Il Shim
• Original Assignee: Hansoo Kim, Sung-Min Hwang, Sun-Il Shim
• Inventors: HWANG, Sung-Min, KIM, Hansoo, SHIM, Sun-Il
• Granted Patent: US 9,208,885 B2
• Time in Patent Office: Days
• US Class Current: 365/185.05
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes.

Claims

1-8. -8. (canceled)

9. A semiconductor memory device comprising:

a semiconductor region extending vertically from a first region of a substrate;

a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, the plurality of gate electrodes being separated from one another and being disposed along a sidewall of the semiconductor region;

a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes;

a substrate contact electrode extending vertically from an impurity-doped second region of the substrate,

the substrate contact electrode extending from the substrate to a height greater than that of an uppermost gate electrode from among the plurality of gate electrodes; and

an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes.

10. The semiconductor memory device of claim 9, wherein the substrate contact electrode extends from the substrate to a height less than the height of a gate electrode of a lowermost memory cell transistor from among memory cell transistors of a memory cell string.

11. The semiconductor memory device of claim 9, further comprising:

an insulating pillar extending vertically from the first region of the substrate;

wherein sidewalls and an upper surface of the insulating pillar are covered by the semiconductor region.

12. The semiconductor memory device of claim 9, wherein the gate dielectric layer comprises:

a tunnel insulating layer, a charge storage layer and a barrier insulating layer that are sequentially stacked on the semiconductor region.

13. The semiconductor memory device of claim 9, wherein the gate dielectric layer is disposed to extend vertically from the substrate along the sidewall of the semiconductor region.

14. The semiconductor memory device of claim 9, wherein the gate dielectric layer is disposed to cover upper and lower surfaces of the plurality of gate electrodes.

15. The semiconductor memory device of claim 9, wherein the gate dielectric layer is disposed between the substrate and a lowermost gate electrode from among the plurality of gate electrodes, and wherein a region of the substrate between the semiconductor region and the impurity-doped second region serves as a channel of a transistor including the lowermost gate electrode.

16. The semiconductor memory device of claim 9, wherein edge regions of the impurity-doped second region of the substrate have a height greater than that of a lower surface of the substrate contact electrode.

17-19. -19. (canceled)

20. A semiconductor memory device comprising:

a memory cell string extending vertically from a first region of a substrate;

a substrate contact electrode disposed on a second region of the substrate; and

an insulating region formed as an air gap between the memory cell string and the substrate contact electrode.

21. A semiconductor memory device having a three-dimensional structure, the semiconductor memory device comprising:

at least one memory cell string disposed on a first region of a surface of a substrate and extending in a first direction, the first direction being substantially perpendicular to the surface of the substrate;

at least one substrate contact electrode disposed on a second region of the substrate and extending in the first direction,

the substrate contact electrode being insulated from the at least one memory cell string by an air gap; and

one of a core circuit unit, a controller, and a processor connected to the semiconductor memory device.

29. A memory device comprising:

a NAND cell array including at least one semiconductor memory device of claim 21;

wherein the core circuit unit is connected to the at least one semiconductor memory device, the core circuit unit is configured to communicate with the NAND cell array, and the core circuit includes including,

a row decoder configured to communicate with the NAND cell array via a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines,

a column decoder configured to communicate with the NAND cell array via a plurality of bit lines,

a sense amplifier configured to communicate with the column decoder, and

a control logic unit configured to communicate with the row decoder and the column decoder.

30. A memory card comprising:

a memory unit including at least one semiconductor memory device of claim 21, wherein the controller is connected to the at least one semiconductor memory device and

the controller is configured to exchange electrical signals with the memory unit.

31. An electronic system comprising:

an input/output unit configured to input data to or output data from the electronic system; and

a memory unit including at least one semiconductor memory device of claim 21, wherein

the processor is connected to the at least one semiconductor memory device,

the memory unit is configured to store at least one of code and data for operating the processor, and

the processor, the input/output unit and the memory unit are coupled to one another via a bus.

22-28. -28. (canceled)