SEMICONDUCTOR MEMORY APPARATUS

• US 20130286738A1
• Filed: 03/15/2013
• Published: 10/31/2013
• Est. Priority Date: 04/27/2012
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KAMATA, Yoshihiko
• Granted Patent: US 9,147,481 B2
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

According to one embodiment, a semiconductor memory apparatus includes an array, a source, a bit line, a sense, and current circuit. The array includes a NAND string. The NAND string includes memory cell. The sense includes a first transistor. One end of transistor is connected to a first node, and other end of the transistor is connected to a second. The first node is used for reading the data held by the memory cell. An internal voltage is smaller than the source voltage. The current circuit outputs a first voltage to a gate of the transistor, and the first voltage is smaller than the internal voltage. The transistor limits a first current from the source to the sense based on a threshold voltage of the memory cell to be read.

Claims

1. A semiconductor memory apparatus comprising:

a memory cell array including a NAND string, the NAND string including memory cell;

a source connected to the NAND string, a source voltage being supplied to the source;

a bit line connected to the NAND string;

a sense amplifier including a first transistor, one end of a current path of the first transistor being connected to a first node, other end of the current path of the first transistor being connected to a second node, the first node being used for reading the data held by the memory cell, an internal voltage being supplied to the second node, the internal voltage being smaller than the source voltage; and

a current source circuit configured to output a first voltage to a gate of the first transistor, the first voltage being smaller than the internal voltage;

wherein when the data is read, the first transistor limits a first current from the source to the sense amplifier based on a threshold voltage of the memory cell to be read while a second voltage is supplied to the source.

2. The apparatus according to claim 1, wherein

the second node is at a zero voltage.

3. The apparatus according to claim 1, wherein

the voltage of the second node is raised to decrease a voltage between a drain and the source of the memory cell to be read.

4. The apparatus according to claim 2, further comprising:

a detector configured to detect the read data; and

a transfer transistor configured to transfer the voltage of the first node to the detector, wherein

a voltage supplied to a gate of the transfer transistor is a value in accordance with current-voltage characteristics of the first current and the second current.

5. The apparatus according to claim 3, further comprising:

a detector configured to detect the read data; and

a transfer transistor configured to transfer the voltage of the first node to the detector, wherein

a voltage supplied to a gate of the transfer transistor is a value in accordance with current-voltage characteristics of the first current and the second current.

6. The apparatus according to claim 1, wherein

the NAND string includes a first memory cell and a second memory cell, one of the first memory cell and the second memory cell being selected, and

when the data is read, a third voltage is supplied to the first memory cell and a fourth voltage is supplied to the second memory cell.

7. A semiconductor memory apparatus comprising:

a memory cell array including a NAND string, the NAND string including memory cell;

a bit line connected to the NAND strings; and

a sense amplifier including a first transistor, one end of a current path of the first transistor being connected to a first node, other end of the current path of the first transistor being connected to a second node, the first node being used for reading the data held by the memory cell, an internal voltage being supplied to the second node;

wherein the sense amplifiers read the voltage of the first node to turning on the first MOS transistor by applying a first voltage to a source of the NAND string while transferring a read voltage to gates of the memory cells constituting the NAND string,

a source voltage is supplied to the source, and

the internal voltage is smaller than the source voltage.

8. The apparatus according to claim 7, wherein

the second node is at a ground voltage.

9. The apparatus according to claim 7, wherein

the second node is at a second voltage which is higher than a ground voltage and lower than the first voltage.

10. The apparatus according to claim 8, wherein

the first node is a third voltage or a fourth voltage higher than the third voltage according to the characteristic of the memory cell and

the first MOS transistor is supplied to “

L”

when the voltage of the first node falls to the third voltage or less.

11. The apparatus according to claim 9, wherein

the first node is a third voltage or a fourth voltage higher than the third voltage according to the characteristic of the memory cell and

the first MOS transistor is supplied to “

L”

when the voltage of the first node falls to the third voltage or less.

12. The apparatus according to claim 8, further comprising:

a detector configured to detect the read data; and

a transfer transistor configured to transfer the voltage of the first node to the detector, wherein

a voltage supplied to a gate of the transfer transistor is a value in accordance with current-voltage characteristics of a first current or a second current and a third current passed by the first MOS transistor.

13. The apparatus according to claim 9, further comprising:

a detector configured to detect the read data; and

a transfer transistor configured to transfer the voltage of the first node to the detector, wherein

a voltage supplied to a gate of the transfer transistor is a value in accordance with current-voltage characteristics of a first current or a second current and a third current passed by the first MOS transistor.

14. A semiconductor memory apparatus comprising:

a memory cell array including a NAND string, the NAND string including memory cell;

a source connected to the NAND string, a source voltage being supplied to the source;

a bit line connected to the NAND string;

a current source circuit configured to include a reference cell having a negative threshold and passing a first current; and

a sense amplifier including a first transistor, one end of a current path of the first transistor being connected to a first node, other end of the current path of the first transistor being connected to a second node, the first node being used for reading the data held by the memory cell, the first transistor configuring a mirror circuit together with the reference cell, an internal voltage being supplied to the second node, the internal voltage being smaller than the source voltage.

15. The apparatus according to claim 14, wherein

the second node is at a zero voltage.

16. The apparatus according to claim 14, wherein

whether the first node shares charges is decided based on whether a threshold of the memory cell from which the data is attempted to be read is larger than the negative threshold of the reference cell.

17. The apparatus according to claim 14, wherein

a determination threshold to read the data held by the memory cell is shifted by varying the negative threshold of the reference cell.

18. The apparatus according to claim 14, wherein

the voltage of the second node is raised to decrease a voltage between a drain and the source of the memory cell to be read.