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SEMICONDUCTOR MEMORY APPARATUS

  • US 20130286738A1
  • Filed: 03/15/2013
  • Published: 10/31/2013
  • Est. Priority Date: 04/27/2012
  • Status: Active Grant
First Claim
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1. A semiconductor memory apparatus comprising:

  • a memory cell array including a NAND string, the NAND string including memory cell;

    a source connected to the NAND string, a source voltage being supplied to the source;

    a bit line connected to the NAND string;

    a sense amplifier including a first transistor, one end of a current path of the first transistor being connected to a first node, other end of the current path of the first transistor being connected to a second node, the first node being used for reading the data held by the memory cell, an internal voltage being supplied to the second node, the internal voltage being smaller than the source voltage; and

    a current source circuit configured to output a first voltage to a gate of the first transistor, the first voltage being smaller than the internal voltage;

    wherein when the data is read, the first transistor limits a first current from the source to the sense amplifier based on a threshold voltage of the memory cell to be read while a second voltage is supplied to the source.

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