SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF

• US 20130286757A1
• Filed: 04/17/2013
• Published: 10/31/2013
• Est. Priority Date: 04/25/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko
• Granted Patent: US 9,230,683 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/045 Floating gate memory cells with both P and N channel memory transistors, usually sharing a common floating gate
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

An error of stored data is detected with high accuracy. Data (e.g., a remainder in a CRC) used for detecting an error is stored in a memory in which an error is unlikely to occur. Specifically, the following semiconductor device is used: a memory element including a plurality of transistors, a capacitor, and a data storage portion is provided in a matrix; the data storage portion includes one of a source and a drain of one of the plurality of transistors, a gate of another one of the plurality of transistors, and one electrode of the capacitor; a semiconductor layer including a channel of the transistor, the one of the source and the drain of which is connected to the data storage portion, has a band gap of 2.8 eV or more, or 3.2 eV or more; and the data storage portion stores data for detecting an error.

Claims

1. A semiconductor device comprising:

a plurality of memory elements being in a matrix, each memory element including;

a plurality of transistors;

a capacitor; and

a data storage portion configured to store data for an error detection,

wherein the data storage portion includes one of a source and a drain of first one of the plurality of transistors, a gate of second one of the plurality of transistors, and a first electrode of the capacitor, and

wherein the first one of the plurality of transistors comprises an oxide semiconductor layer.

2. The semiconductor device according to claim 1,

wherein the error detection is a cyclic redundancy check, and

wherein the data for the error detection is a remainder used for the cyclic redundancy check.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer in the first one of the plurality of transistors has a thickness of 20 nm or less.

4. The semiconductor device according to claim 1, wherein one of a source and a drain of the second one of the plurality of transistors is connected to one of a source and a drain of third one of the plurality of transistors.

5. The semiconductor device according to claim 1, wherein a second electrode of the capacitor is connected to one of a source and a drain of fourth one of the plurality of transistors.

6. The semiconductor device according to claim 1, wherein the data storage portion further includes a gate of third one of the plurality of transistors.

7. The semiconductor device according to claim 1, wherein the capacitor has a capacitance of 1 fF or more.

8. A method for driving a semiconductor device comprising the steps of:

calculating a remainder;

storing the remainder in a cyclic redundancy check memory;

detecting an error of an i-th row with use of the remainder by a cyclic redundancy check;

performing processing of an i+1-th row if there is no error in the i-th row;

writing data to be input to the i-th row which is stored in a configuration memory if there is an error in the i-th row; and

repeating the step of detecting an error and the step of writing data until no error is detected,

wherein the cyclic redundancy check memory has a lower error rate than the configuration memory.

9. The method for driving a semiconductor device, according to claim 8, wherein data of the i-th row is taken out from a boot memory when calculating the remainder.

10. The method for driving a semiconductor device, according to claim 8, wherein the cyclic redundancy check is performed by the steps of:

adding data of the i-th row of the cyclic redundancy check memory to end of data of the i-th row of the configuration memory;

dividing a sum of the data of the i-th row of the cyclic redundancy check memory to the end of the data of the i-th row of the configuration memory by a predetermined divisor; and

determining whether the remainder is 0.

11. The method for driving a semiconductor device, according to claim 8, wherein in the case where the step of detecting an error with use of the remainder is repeated a predetermined number of times or more, the remainder is calculated again.

12. The method for driving a semiconductor device, according to claim 8, wherein a divisor used for calculating the remainder is stored in a ROM.

13. The method for driving a semiconductor device, according to claim 8, wherein the cyclic redundancy check memory is provided in the semiconductor device comprising:

a plurality of memory elements being in a matrix, each memory element including;

a plurality of transistors;

a capacitor; and

a data storage portion configured to store data for an error detection,

wherein the data storage portion includes one of a source and a drain of first one of the plurality of transistors, a gate of second one of the plurality of transistors, and a first electrode of the capacitor, and

wherein the first one of the plurality of transistors comprises an oxide semiconductor layer.

14. A readable memory device storing a computer program for detecting an error in a memory of a semiconductor device, when the computer program is executed in the semiconductor device or a processor, the semiconductor device or the processor conducting the steps of:

calculating a remainder;

storing the remainder in a cyclic redundancy check memory;

detecting an error of an i-th row with use of the remainder by a cyclic redundancy check;

performing processing of an i+1-th row when there is no error in the i-th row;

writing data to be input to the i-th row which is stored in a configuration memory when there is an error in the i-th row; and

repeating the step of detecting an error and the step of writing data until no error is detected,

wherein the cyclic redundancy check memory has a lower error rate than the configuration memory.

15. The readable memory device according to claim 14, wherein data of the i-th row is taken out from a boot memory when calculating the remainder.

16. The readable memory device according to claim 14, wherein the cyclic redundancy check is performed by the steps of:

adding data of the i-th row of the cyclic redundancy check memory to end of data of the i-th row of the configuration memory;

dividing a sum of the data of the i-th row of the cyclic redundancy check memory to the end of the data of the i-th row of the configuration memory by a predetermined divisor; and

determining whether the remainder is 0.

17. The readable memory device according to claim 14, wherein a divisor used for calculating the remainder is stored in a ROM.

18. The readable memory device according to claim 14, wherein the cyclic redundancy check memory is provided in the semiconductor device comprising:

a plurality of memory elements being in a matrix, each memory element including;

a plurality of transistors;

a capacitor; and

a data storage portion configured to store data for an error detection,

wherein the data storage portion includes one of a source and a drain of first one of the plurality of transistors, a gate of second one of the plurality of transistors, and a first electrode of the capacitor, and

wherein the first one of the plurality of transistors comprises an oxide semiconductor layer.