Methods for Reduced Gate Resistance FINFET
First Claim
1. A method comprising:
- forming multiple semiconductor fins over a semiconductor substrate, the multiple semiconductor fins spaced apart;
forming a metal containing gate electrode overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins;
forming an interlevel dielectric layer overlying the metal containing gate electrode and the semiconductor substrate;
forming a plurality of contacts extending through the interlevel dielectric layer to the metal containing gate electrode, each of the plurality of contacts spaced from the channel gate regions of the semiconductor fins; and
forming a metal strap layer over the interlevel dielectric layer coupled to the metal containing gate electrode through the plurality of contacts.
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Abstract
Methods for forming reduced gate resistance finFETs. Methods for a metal gate transistor structure are disclosed including forming a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Additional methods are disclosed.
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Citations
20 Claims
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1. A method comprising:
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forming multiple semiconductor fins over a semiconductor substrate, the multiple semiconductor fins spaced apart; forming a metal containing gate electrode overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; forming an interlevel dielectric layer overlying the metal containing gate electrode and the semiconductor substrate; forming a plurality of contacts extending through the interlevel dielectric layer to the metal containing gate electrode, each of the plurality of contacts spaced from the channel gate regions of the semiconductor fins; and forming a metal strap layer over the interlevel dielectric layer coupled to the metal containing gate electrode through the plurality of contacts. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for forming a multiple fin finFET device, comprising:
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forming multiple semiconductor fins over a semiconductor substrate, the multiple semiconductor fins spaced apart; forming a gate dielectric layer over the multiple semiconductor fins to define a channel gate region of each of the multiple semiconductor fins forming a metal containing gate electrode overlying a channel gate region of each of the multiple semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; forming an interlevel dielectric layer overlying the metal containing gate electrode and the semiconductor substrate; forming a plurality of vertical contacts extending through the interlevel dielectric layer to the metal containing gate electrode, each of the plurality of vertical contacts spaced from the channel gate regions of the semiconductor fins; and forming a metal strap layer over the interlevel dielectric layer coupled to the metal containing gate electrode through the plurality of contacts. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A method for forming a finFET device, comprising:
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providing a semiconductor substrate; patterning the semiconductor substrate to form multiple semiconductor fins in parallel and spaced apart one from another; depositing a gate dielectric over the multiple semiconductor fins; depositing a metal containing gate electrode over the gate dielectric; patterning the gate dielectric and the metal containing gate electrode to form channel gate regions over the multiple semiconductor fins; forming an interlevel dielectric layer overlying the metal containing gate electrode and the semiconductor substrate; forming a plurality of vertical contacts extending through the interlevel dielectric layer to the metal containing gate electrode, each of the plurality of vertical contacts spaced from the channel gate regions of the semiconductor fins; and forming a metal strap layer over the interlevel dielectric layer coupled to the metal containing gate electrode through the plurality of contacts. - View Dependent Claims (18, 19, 20)
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Specification