APPARATUS AND METHOD OF MASK PERMUTE INSTRUCTIONS

• US 20130290672A1
• Filed: 12/23/2011
• Published: 10/31/2013
• Est. Priority Date: 12/23/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ould-Ahmed-Vall, Elmoustapha, Valentine, Robert, Corbal, Jesus, Sair, Suleyman
• Granted Patent: US 9,632,980 B2
• Time in Patent Office: Days
• US Class Current: 712/7
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields

Abstract

An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

Claims

1. An apparatus, comprising:

instruction execution logic circuitry having;

input vector element routing circuitry to perform the following for each of three different instructions;

for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source said output vector element, said output vector element and each of said input vector element locations being one of three available bit widths for said three different instructions; and

,

masking layer circuitry coupled to said input vector element routing circuitry to mask a data structure created by said input vector routing element circuitry, said masking layer circuitry designed to mask at three different levels of granularity that correspond to said three available bit widths.

2. The apparatus of claim 1 wherein said input vector element routing circuitry is designed to, for each of said three available bit widths:

route said input vector element from all input vector locations of said input vector.

3. The apparatus of claim 2 wherein said input vector element routing circuitry is further designed to perform the following for additional instructions other than said three different instructions:

for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source said output vector element, said plurality of input vector locations corresponding to a section of said input vector that is smaller than said input vector.

4. The apparatus of claim 3 wherein:

for a first of said additional instructions, said output vector element and each of said input vector element locations are one of said three available bit widths; and

,

for a second of said additional instructions, said output vector element and each of said input vector element locations are another one of said three available bit widths.

5. The apparatus of claim 4 wherein, said section for said first of said additional instructions and said section for said second of said additional instructions are the same size.

6. The apparatus of claim 5 wherein said section for said first and second additional instructions is one quarter of a maximum resultant vector size for any of said instructions.

7. The apparatus of claim 1 wherein said input vector element routing circuitry is further designed to perform the following for additional instructions other than said three different instructions:

for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source said output vector element, said plurality of input vector locations corresponding to a portion of said input vector that is smaller than said input vector, and, said available input vector elements do not neighbor one another within said input vector.

8. A method, comprising:

performing the following by executing instructions through a same instruction execution pipeline;

in executing first, second and third instructions, for each of first, second and third vector element sizes;

routing into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source said output vector element for each of a plurality of output vector element locations; and

,

mask respective resultants of said routing at a granularity that corresponds to first, second and third vector element sizes.

9. The method of claim 8 where, said input vector element locations correspond to all input vector locations of said input vector.

10. The method of claim 9 further comprising executing fourth and fifth instructions for said first and second vector element sizes respectively, said fourth and fifth instructions including routing into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source said output vector element for each of a plurality of output vector element locations, wherein, said input vector element locations that are available to source said output vector element correspond to a section of said input vector that is smaller than said input vector.

11. The method of claim 9 further comprising executing sixth and seventh instructions for said first and second vector element sizes respectively, said sixth and seventh instructions including routing into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source said output vector element for each of a plurality of output vector element locations, wherein, said input vector element locations that are available to source said output vector element correspond to a portion of said input vector that is smaller than said input vector, and, do not neighbor one another within said input vector.

12. The method of claim 11 wherein said first and second vector element sizes are 32 and 64 bits respectively.

13. The method of claim 8 wherein said first, second and third vector element sizes are 16, 32 and 64 bits respectively.

14. The method of claim 8 wherein a maximum input vector size is 512 bits.

15. An apparatus, comprising:

instruction execution logic circuitry having;

input vector element routing circuitry to perform the following for each of three different instructions;

for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source said output vector element, said output vector element and each of said input vector element locations being one of three available bit widths for said three different instructions, an index vector specifying routing of elements from said input vector to said output vector for a first of said instructions, an immediate operand specifying routing of elements from said input vector to said output vector for a second of said instructions; and

,

masking layer circuitry coupled to said input vector element routing circuitry to mask a data structure created by said input vector routing element circuitry, said masking layer circuitry designed to mask at three different levels of granularity that correspond to said three available bit widths.

16. The apparatus of claim 15 wherein said input vector element routing circuitry is designed to, for each of said three available bit widths:

route said input vector element from all input vector locations of said input vector.

17. The apparatus of claim 16 wherein said input vector element routing circuitry is further designed to perform the following for additional instructions other than said three different instructions:

for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source said output vector element, said plurality of input vector locations corresponding to a section of said input vector that is smaller than said input vector.

18. The apparatus of claim 17 wherein:

for a first of said additional instructions, said output vector element and each of said input vector element locations are one of said three available bit widths; and

,

for a second of said additional instructions, said output vector element and each of said input vector element locations are another one of said three available bit widths.

19. The apparatus of claim 18 wherein, said section for said first of said additional instructions and said section for said second of said additional instructions are the same size.

20. The apparatus of claim 16 wherein one of said bit widths is 32 bits and another of said bit widths is 64 bits.