APPARATUS AND METHOD OF MASK PERMUTE INSTRUCTIONS
First Claim
1. An apparatus, comprising:
- instruction execution logic circuitry having;
input vector element routing circuitry to perform the following for each of three different instructions;
for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source said output vector element, said output vector element and each of said input vector element locations being one of three available bit widths for said three different instructions; and
,masking layer circuitry coupled to said input vector element routing circuitry to mask a data structure created by said input vector routing element circuitry, said masking layer circuitry designed to mask at three different levels of granularity that correspond to said three available bit widths.
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Abstract
An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.
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Citations
20 Claims
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1. An apparatus, comprising:
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instruction execution logic circuitry having; input vector element routing circuitry to perform the following for each of three different instructions;
for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source said output vector element, said output vector element and each of said input vector element locations being one of three available bit widths for said three different instructions; and
,masking layer circuitry coupled to said input vector element routing circuitry to mask a data structure created by said input vector routing element circuitry, said masking layer circuitry designed to mask at three different levels of granularity that correspond to said three available bit widths. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method, comprising:
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performing the following by executing instructions through a same instruction execution pipeline; in executing first, second and third instructions, for each of first, second and third vector element sizes; routing into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source said output vector element for each of a plurality of output vector element locations; and
,mask respective resultants of said routing at a granularity that corresponds to first, second and third vector element sizes. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. An apparatus, comprising:
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instruction execution logic circuitry having; input vector element routing circuitry to perform the following for each of three different instructions;
for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source said output vector element, said output vector element and each of said input vector element locations being one of three available bit widths for said three different instructions, an index vector specifying routing of elements from said input vector to said output vector for a first of said instructions, an immediate operand specifying routing of elements from said input vector to said output vector for a second of said instructions; and
,masking layer circuitry coupled to said input vector element routing circuitry to mask a data structure created by said input vector routing element circuitry, said masking layer circuitry designed to mask at three different levels of granularity that correspond to said three available bit widths. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification