SEMICONDUCTOR DEVICE

• US 20130292671A1
• Filed: 07/11/2013
• Published: 11/07/2013
• Est. Priority Date: 10/30/2009
• Status: Abandoned Application

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, KOYAMA, Jun, KATO, Kiyoshi
• Application Number:
  US13/939,223
• Publication Number:
  US 20130292671A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

It is an object to provide a semiconductor having a novel structure. In the semiconductor device, a plurality of memory elements are connected in series and each of the plurality of memory elements includes first to third transistors thus forming a memory circuit. A source or a drain of a first transistor which includes an oxide semiconductor layer is in electrical contact with a gate of one of a second and a third transistor. The extremely low off current of a first transistor containing the oxide semiconductor layer allows storing, for long periods of time, electrical charges in the gate electrode of one of the second and the third transistor, whereby a substantially permanent memory effect can be obtained. The second and the third transistors which do not contain an oxide semiconductor layer allow high-speed operations when using the memory circuit.

Claims

1. (canceled)

2. A semiconductor device comprising:

a substrate including a semiconductor material;

a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, one of the second drain electrode and the second source electrode being electrically connected to the first gate electrode; and

a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode, one of the third source electrode and the third drain electrode being electrically connected to one of the first source electrode and the first drain electrode, and the other of the third source electrode and the third drain electrode being electrically connected to the other of the first source electrode and the first drain electrode,

wherein a channel formation region of the first transistor is comprised in the substrate, and

wherein the second transistor includes an oxide semiconductor layer, a channel formation region of the second transistor being comprised in the oxide semiconductor layer.

8. The semiconductor device according to claim 2, wherein the substrate including the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

11. The semiconductor device according to claim 2, wherein the oxide semiconductor layer includes an In—

Ga—

Zn—

O-based oxide semiconductor material.

14. The semiconductor device according to claim 2, wherein a concentration of hydrogen of the oxide semiconductor layer is 5×

10¹⁹ atoms/cm³ or less.

17. The semiconductor device according to claim 2, wherein an off-state current of the second transistor is 1×

10<sup>−

13</sup> A or less.

3. A semiconductor device comprising:

a substrate;

a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;

a first interlayer insulating layer over the first transistor;

a second transistor over the first interlayer insulating layer, the second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, one of the second drain electrode and the second source electrode being electrically connected to the first gate electrode;

a second interlayer insulating layer over the second transistor;

an electrode over the second interlayer insulating layer; and

a third transistor comprising a third gate electrode, a third source electrode, and

a third drain electrode, one of the third source electrode and the third drain electrode being electrically connected to one of the first source electrode and the first drain electrode, and the other of the third source electrode and the third drain electrode being electrically connected to the other of the first source electrode and the first drain electrode,

wherein the first gate electrode is electrically connected to the one of the second source electrode and the second drain electrode via the electrode.

4. The semiconductor device according to claim 3,

wherein a channel formation region of the first transistor is comprised in the substrate, and

wherein the second transistor includes an oxide semiconductor layer, a channel formation region of the second transistor being comprised in the oxide semiconductor layer.

7. The semiconductor device according to claim 4,

wherein channel formation regions of the first transistors are comprised in the substrate, and

wherein the second transistors include oxide semiconductor layers, channel formation regions of the second transistors being comprised in corresponding oxide semiconductor layers.

9. The semiconductor device according to claim 4, wherein the substrate including the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

12. The semiconductor device according to claim 4, wherein the oxide semiconductor layer includes an In—

Ga—

Zn—

O-based oxide semiconductor material.

15. The semiconductor device according to claim 4, wherein a concentration of hydrogen of the oxide semiconductor layer is 5×

10¹⁹ atoms/cm³ or less.

18. The semiconductor device according to claim 4, wherein an off-state current of the second transistor is 1×

10<sup>−

13</sup> A or less.

5. A semiconductor device comprising:

a substrate;

a first wiring;

a second wiring;

a plurality of third wirings;

a plurality of fourth wirings;

a plurality of fifth wirings;

a first interlayer insulating layer;

a second interlayer insulating layer; and

a plurality of memory elements connected in series between the first wiring and the second wiring, each memory element comprising;

a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;

the first interlayer insulating layer over the first transistor;

a second transistor over the first interlayer insulating layer, the second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, one of the second drain electrode and the second source electrode being electrically connected to the first gate electrode;

the second interlayer insulating layer over the second transistor;

an electrode over the second interlayer insulating layer; and

a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode, one of the third source electrode and the third drain electrode being electrically connected to one of the first source electrode and the first drain electrode, and the other of the third source electrode and the third drain electrode being electrically connected to the other of the first source electrode and the first drain electrode,

wherein the first wiring, the first source electrode, and the third source electrode are electrically connected to each other,

wherein the first wiring is electrically connected to one of the first source electrode and the first drain electrode of a first outermost one of the memory elements through an electrical path that does not go through a channel formation region of the first transistor of the first outermost one of the memory elements or through a channel formation region of the third transistor of the first outermost one of the memory elements,

wherein the second wiring is electrically connected to one of the first source electrode and the first drain electrode of a second outermost one of the memory elements through an electrical path that does not go through a channel formation region of the first transistor of the second outermost one of the memory elements or through a channel formation region of the third transistor of the second outermost one of the memory elements,

wherein the third wirings are electrically connected to corresponding second source electrodes or second drain electrodes,

wherein the fourth wirings are electrically connected to the second gate electrodes,

wherein the fifth wirings are electrically connected to corresponding third gate electrodes, and

wherein the first gate electrodes are electrically connected to corresponding second source electrodes or second drain electrodes via corresponding electrodes.

6. The semiconductor device according to claim 5, further comprising:

a fourth transistor comprising; and

a fifth transistor,

wherein the memory elements are electrically connected to the first wiring through the fourth transistor and to the second wiring through the fifth transistor.

10. The semiconductor device according to claim 6, wherein the substrate including the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

13. The semiconductor device according to claim 6, wherein the oxide semiconductor layers include an In—

Ga—

Zn—

O-based oxide semiconductor material.

16. The semiconductor device according to claim 6, wherein concentrations of hydrogen of the oxide semiconductor layers are 5×

10¹⁹ atoms/cm³ or less.

19. The semiconductor device according to claim 6, wherein off-state currents of the second transistors are 1×

10<sup>−

13</sup> A or less.