SEMICONDUCTOR PACKAGE INTEGRATED WITH CONFORMAL SHIELD AND ANTENNA

• US 20130292808A1
• Filed: 05/04/2012
• Published: 11/07/2013
• Est. Priority Date: 05/04/2012
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Liao, Kuo-Hsien, Yen, Han-Chee, Chung, Chi-Sheng, Yeh, Yung-I
• Granted Patent: US 8,786,060 B2
• Time in Patent Office: Days
• US Class Current: 257/660
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01Q 1/2283 : mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 23/00 : Antennas with active circuits or circuit elements integrated within them or attached to them
• CPC Class Codes: H01Q 9/0407 : Substantially flat resonant element parallel to ground plane, e.g. patch antenna dipole H01Q9/285; monopole H01Q9/40

Abstract

A semiconductor package includes a substrate, a semiconductor die, a package body, an electromagnetic interference shield, a dielectric structure and an antenna element. The substrate comprises a grounding segment and a feeding point. The semiconductor die is disposed on the substrate. The package body encapsulates the semiconductor die. The electromagnetic interference shield is formed on the package body. The dielectric structure encapsulates the electromagnetic interference shield. The antenna element is formed on the dielectric structure and electrically connecting the grounding segment of the substrate and the feeding point.

Claims

1. A semiconductor package, comprising:

a substrate;

a semiconductor die disposed on the substrate;

a package body encapsulating the semiconductor die;

an electromagnetic interference shield formed on the package body;

a dielectric structure covering the electromagnetic interference shield;

an antenna formed on the dielectric structure;

a feeding element connecting the antenna and a feeding point of the substrate; and

an antenna grounding element connecting the antenna and the electromagnetic interference shield.

2. The semiconductor package of claim 1, wherein the antenna grounding element is disposed within the dielectric structure.

3. The semiconductor package of claim 1, wherein the feeding element penetrates the package body and the dielectric structure.

4. The semiconductor package of claim 1, wherein the antenna grounding element and the feeding element form an extension portion of the antenna on a lateral surface of the dielectric structure.

5. The semiconductor package of claim 1, further comprising:

a grounding frame disposed on the substrate and connecting the substrate and the electromagnetic interference shield.

6. The semiconductor package of claim 1, further comprising:

a dielectric material layer covering the dielectric structure;

wherein the permittivity of the dielectric material layer is higher than that of the dielectric structure.

7. A semiconductor package, comprising:

a semiconductor die, the semiconductor die having an integrated circuit portion and a substrate portion, the integrated circuit portion having an active surface and the substrate portion having an inactive surface;

a via extending from the inactive surface and electrically connected to the integrated circuit portion;

an electromagnetic interference shield disposed on the inactive surface and electrically connected to the via;

a package body encapsulating portions of the die and the electromagnetic interference shield, the package body having an upper surface;

a feeding element penetrating the package body and the substrate portion, and electrically connected to the integrated circuit portion;

an antenna disposed on the upper surface and electrically connected to the feeding element; and

an antenna grounding element disposed within the package body and connecting the antenna and the electromagnetic interference shield.

8. The semiconductor package of claim 7, wherein the feeding element comprises a first feeding sub-element and a second feeding sub-element, the first feeding sub-element disposed in the substrate portion, and the second feeding sub-element disposed in the package body.

9. The semiconductor package of claim 8, wherein the first feeding sub-element is a through silicon via.

10. The semiconductor package of claim 7, wherein the via is a through silicon via formed in the substrate portion.

11. The semiconductor package according to claim 7, wherein the package body has an opening from which the feeding element is exposed.

12. The semiconductor package of claim 7, wherein the feeding element does not directly contact the electromagnetic shield.

13. The semiconductor package of claim 7, further including a redistribution layer (RDL) disposed on the active surface and electrically connected thereto.

14. The semiconductor package of claim 7, further comprising:

a grounding frame disposed on the substrate portion and connecting the substrate portion and the electromagnetic interference shield.

15. The semiconductor package of claim 7, further comprising:

a dielectric material layer covering at least part of the dielectric structure;

wherein the permittivity of the dielectric material layer is higher than that of the dielectric structure.

16. The semiconductor package of claim 7, wherein the antenna grounding element and the feeding element form an extension portion of the antenna on a lateral surface of the dielectric structure.

17. A semiconductor package, comprising:

a semiconductor die, the semiconductor die having an integrated circuit portion and a substrate portion, the integrated circuit portion having an active surface and the substrate portion having an inactive surface;

a first conductive via and a second conductive via, each formed in the die and electrically connected to the integrated circuit portion;

an electromagnetic interference shield disposed on the inactive surface and electrically connected to the first conductive via;

a dielectric layer disposed on the electromagnetic interference shield, the dielectric layer having an upper surface;

a feeding element, wherein the feeding element comprises a first feeding sub-element and a second feeding sub-element, the first feeding sub-element being the second conductive via, and the second feeding sub-element disposed in the package body;

an antenna disposed on the upper surface and electrically connected to the feeding element; and

an antenna grounding element connecting the antenna and the electromagnetic interference shield.

18. The semiconductor package of claim 17, wherein the feeding element does not directly contact the electromagnetic shield.

19. The semiconductor package of claim 17, wherein the dielectric layer has an opening from which the feeding element is exposed.

20. The semiconductor package of claim 17, further including a redistribution layer (RDL) disposed on the active surface and electrically connected thereto.