Contactless Wafer Probing with Improved Power Supply
First Claim
1. An integrated circuit, comprising:
- an inductive or capacitive wireless communication structure located on a die region of the integrated circuit and configured to wirelessly receive a test stimulus vector to test circuitry on the die region; and
a landing region having a size and location suitable to allow a conductive needle or conductive probe to come into direct physical and electrical contact with the landing region to provide a DC power supply to the circuitry on the die region while the test stimulus vector is wirelessly received.
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Accused Products
Abstract
Some embodiments relate to an integrated circuit. The integrated circuit includes an inductive or capacitive wireless communication structure located on a die region of the integrated circuit. This wireless communication structure is configured to wirelessly receive a test stimulus vector to test circuitry on the die region. The integrated circuit also includes a landing region having a size and location suitable to allow a conductive needle or conductive probe to come into direct physical and electrical contact with the landing region. The landing region provides a DC power supply to the circuitry on the die region while the test stimulus vector is wirelessly received.
5 Citations
20 Claims
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1. An integrated circuit, comprising:
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an inductive or capacitive wireless communication structure located on a die region of the integrated circuit and configured to wirelessly receive a test stimulus vector to test circuitry on the die region; and a landing region having a size and location suitable to allow a conductive needle or conductive probe to come into direct physical and electrical contact with the landing region to provide a DC power supply to the circuitry on the die region while the test stimulus vector is wirelessly received. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor wafer, comprising:
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a plurality of die regions, wherein respective die regions include respective integrated circuit structures corresponding thereto; scribe lines arranged between neighboring die regions; a power bus arranged in a scribe line and coupled to the respective integrated circuit structures in the plurality of die regions; and respective inductive or capacitive communication structures arranged on respective die regions;
wherein an inductive or capacitive communication structure on a die region is configured to wirelessly receive a test stimulus vector to an integrated circuit structure on the die region. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A method of automated testing for a semiconductor wafer, comprising:
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placing a conductive power conduit in physical and electrical contact with a power bus on the wafer; supplying a DC power to integrated circuit structures on the wafer via the conductive power conduit and the power bus; and while the DC power is supplied to the integrated circuit structures, wirelessly transmitting stimulus test vectors to the integrated circuit structures to test functionality of the integrated circuit structures. - View Dependent Claims (17, 18, 19, 20)
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Specification