Method and Apparatus for use in Improving Linearity of MOSFETs using an Accumulated Charge Sink

• US 20130293280A1
• Filed: 03/25/2013
• Published: 11/07/2013
• Est. Priority Date: 07/11/2005
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Brindle, Christopher N., Stuber, Michael A., Kelly, Dylan J., Kemerling, Clint L., Imthurn, George, Welstand, Robert B., Burgener, Mark L.
• Granted Patent: US 9,130,564 B2
• Time in Patent Office: Days
• US Class Current: 327/382
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Claims

1. An RF switch, comprising:

a first RF port;

a second RF port;

a first switch transistor grouping coupled to the first RF port and to the second RF port and comprising a first plurality of switch NMOSFETs arranged in a stacked configuration;

a first shunt transistor grouping coupled to the first RF port and to ground and comprising a first plurality of shunt NMOSFETs arranged in a stacked configuration,

wherein at least one of the first plurality of shunt NMOSFETs comprises a first gate, a first source, a first drain, a first body, and a first accumulated charge sink (ACS) coupled to the first body,

wherein a first ACS bias voltage is applied to the first ACS,

wherein the first ACS is in electrical communication with the first body and is configured so that when the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs is operated in an off-state (non-conducting state), the first ACS bias voltage is substantially negative with respect to ground to substantially prevent accumulated charge from accumulating in the first body of the at least one shunt NMOSFET; and

wherein the first switch transistor grouping and the first shunt transistor grouping are fabricated on a silicon-on-insulator substrate.

2. The RF switch of claim 1, wherein preventing accumulated charge from accumulating in the first body of the at least one shunt NMOSFET improves linearity of the at least one shunt NMOSFET.

3. The RF switch of claim 2, wherein the first ACS is positioned proximate a first distal end of the first body.

4. The RF switch of claim 2, wherein the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs further comprises a first electrical contact region, wherein the first electrical contact region and the first ACS are coterminous.

5. The RF switch of claim 4, wherein the first electrical contact region is positioned proximate to and in electrical contact with the first ACS.

6. The RF switch of claim 2, wherein the first ACS is electrically coupled to the gate.

7. The RF switch of claim 2, wherein the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs comprises an enhancement mode NMOSFET.

8. The RF switch of claim 2, wherein the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs comprises a depletion mode NMOSFET.

9. The RF switch of claim 2, 3 or 5, wherein the width of the first body is greater than 10 μ

m.

10. The RF switch of claim 2, 3 or 5, wherein the RF switch is capable of processing input signals having power levels equal to or less than 35 dBm.

11. The RF switch of claim 2, 3 or 5, wherein the first switch transistor grouping and the first shunt transistor grouping are fabricated in a silicon layer having a thickness between about 100 angstroms to about 2,000 angstroms.

12. The RF switch of claim 2, 3 or 5, wherein the first ACS bias voltage applied to the first ACS is negative with respect to ground and has a magnitude of approximately 2.5V in an off-state (non-conducting state).

13. The RF switch of claim 12, wherein the first ACS bias voltage applied to the first ACS has a voltage level in an on-state (conducting state) that is different from a voltage level in an off-state (non-conducting state).

14. The RF switch of claim 1, further comprising:

a third RF port;

a second switch transistor grouping coupled to the third RF port and to the second RF port and comprising a second plurality of switch NMOSFETs arranged in a stacked configuration,

wherein at least one of the second plurality of switch NMOSFETs comprises a second gate, a second source, a second drain, a second body, and a second accumulated charge sink (ACS) coupled to the second body,

wherein a second ACS bias voltage is applied to the second ACS,

wherein the second ACS is in electrical communication with the second body and is configured so that when the at least one switch NMOSFET of the second plurality of switch NMOSFETs is operated in an off-state (non-conducting state), the second ACS bias voltage is substantially negative with respect to ground to substantially prevent accumulated charge from accumulating in the second body of the at least one switch NMOSFET of the second plurality of switch NMOSFETs; and

wherein the second switch transistor grouping is fabricated on the silicon-on-insulator substrate.

15. The RF switch of claim 14, wherein preventing accumulated charge from accumulating in the second body of the at least one switch NMOSFET of the second plurality of switch NMOSFETs improves linearity of the signal passed through to the second RF port.

16. The RF switch of claim 15, wherein the first ACS is positioned proximate a first distal end of the first body and the second ACS is positioned proximate a second distal end of the second body.

17. The RF switch of claim 15, wherein the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs further comprises a first electrical contact region, wherein the first electrical contact region and the first ACS are coterminous, and wherein the at least one switch NMOSFET of the first plurality of switch NMOSFETs further comprises a second electrical contact region, wherein the second electrical contact region and the second ACS are coterminous.

18. The RF switch of claim 17, wherein the first electrical contact region is positioned proximate to and in electrical contact with the first ACS, and wherein the second electrical contact region is positioned proximate to and in electrical contact with the second ACS.

19. The RF switch of claim 15, wherein the first ACS and second ACS are electrically coupled to the gate.

20. The RF switch of claim 15, wherein the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs comprises an enhancement mode NMOSFET.

21. The RF switch of claim 15, wherein the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs comprises a depletion mode NMOSFET.

22. The RF switch of claim 15, 16 or 18, wherein the RF switch is capable of processing input signals having power levels equal to or less than 35 dBm.

23. The RF switch of claim 15, 16 or 18, wherein the width of the first body is greater than 10 μ

m and the width of the second body is greater than 10 μ

m.

24. The RF switch of claim 15, 16 or 18, wherein the first and second switch transistor groupings and the first shunt transistor grouping are fabricated in a silicon layer having a thickness between about 100 angstroms to about 2,000 angstroms.

25. The RF switch of claim 15, 16 or 18, wherein the first ACS bias voltage applied to the first ACS and the second ACS bias voltage applied to the second ACS are negative with respect to ground and have a magnitude of approximately 2.5V in an off-state (non-conducting state).

26. The RF switch of claim 25, wherein the first ACS bias voltage applied to the first ACS and the second ACS bias voltage applied to the second ACS have a voltage level in an on-state (conducting state) that is different from a voltage level in an off-state (non-conducting state).

27. The RF switch of claim 15, 16 or 18, wherein the first and second switch transistor groupings and the first shunt transistor grouping are fabricated in a silicon layer having a thickness of approximately 100 angstroms to approximately 2,000 angstroms, and wherein the first ACS bias voltage applied to the first ACS and the second ACS bias voltage applied to the second ACS are negative with respect to ground and have a magnitude of approximately 2.5V in an off-state (non-conducting state).

28. The RF switch of claim 15, 16 or 18, wherein the first ACS bias voltage and the second ACS bias voltage have the same magnitude.

29. An RF switch, comprising:

a first RF port;

a second RF port;

a first switch transistor grouping coupled to the first RF port and to the second RF port and comprising a first plurality of switch NMOSFETs arranged in a stacked configuration;

a first shunt transistor grouping coupled to the first RF port and to ground and comprising a first plurality of shunt NMOSFETs arranged in a stacked configuration,

wherein at least one of the first plurality of shunt NMOSFETs comprises a first gate, a first source, a first drain, a first body, and a first accumulated charge sink (ACS) coupled to the first body,

wherein a first ACS bias voltage is applied to the first ACS,

wherein the first ACS is in electrical communication with the first body and is configured so that when the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs is operated in an off-state (non-conducting state), the first ACS bias voltage is substantially more negative than the lesser of a first source bias voltage applied to the first source and a first drain bias voltage applied to the first drain to substantially prevent accumulated charge from accumulating in the first body of the at least one shunt NMOSFET; and

wherein the first switch transistor grouping and the first shunt transistor grouping are fabricated on a silicon-on-insulator substrate.

30. The RF switch of claim 29, wherein preventing accumulated charge from accumulating in the first body of the at least one shunt NMOSFET improves linearity of the at least one shunt NMOSFET.

31. The RF switch of claim 30, wherein the first ACS is positioned proximate a first distal end of the first body.

32. The RF switch of claim 30, wherein the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs further comprises a first electrical contact region, wherein the first electrical contact region and the first ACS are coterminous.

33. The RF switch of claim 32, wherein the first electrical contact region is positioned proximate to and in electrical contact with the first ACS.

34. The RF switch of claim 30, wherein the first ACS is electrically coupled to the gate.

35. The RF switch of claim 30, wherein the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs comprises an enhancement mode NMOSFET.

36. The RF switch of claim 30, wherein the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs comprises a depletion mode NMOSFET.

37. The RF switch of claim 30, 31 or 33, wherein the width of the first body is greater than 10 μ

m.

38. The RF switch of claim 30, 31 or 33, wherein the RF switch is capable of processing input signals having power levels equal to or less than 35 dBm.

39. The RF switch of claim 30, 31 or 33, wherein the first switch transistor grouping and the first shunt transistor grouping are fabricated in a silicon layer having a thickness between about 100 angstroms to about 2,000 angstroms.

40. The RF switch of claim 30, 31 or 33, wherein the first ACS bias voltage applied to the first ACS is negative with respect to ground and has a magnitude of approximately 2.5V in an off-state (non-conducting state).

41. The RF switch of claim 40, wherein the first ACS bias voltage applied to the first ACS has a voltage level in an on-state (conducting state) that is different from a voltage level in an off-state (non-conducting state).

42. The RF switch of claim 29, further comprising:

a third RF port;

a second switch transistor grouping coupled to the third RF port and to the second RF port and comprising a second plurality of switch NMOSFETs arranged in a stacked configuration,

wherein at least one of the second plurality of switch NMOSFETs comprises a second gate, a second source, a second drain, a second body, and a second accumulated charge sink (ACS) coupled to the second body,

wherein a second ACS bias voltage is applied to the second ACS,

wherein the second ACS is in electrical communication with the second body and is configured so that when the at least one switch NMOSFET of the second plurality of switch NMOSFETs is operated in an off-state (non-conducting state), the second ACS bias voltage is substantially more negative than the lesser of a second source bias voltage applied to the second source and a second drain bias voltage applied to the second drain to substantially prevent accumulated charge from accumulating in the second body of the at least one switch NMOSFET of the second plurality of switch NMOSFETs; and

wherein the second switch transistor grouping is fabricated on the silicon-on-insulator substrate.

43. The RF switch of claim 42, wherein preventing accumulated charge from accumulating in the second body of the at least one switch NMOSFET of the second plurality of switch NMOSFETs improves linearity of the signal passed through to the second RF port.

44. The RF switch of claim 43, wherein the first ACS is positioned proximate a first distal end of the first body and the second ACS is positioned proximate a second distal end of the second body.

45. The RF switch of claim 43, wherein the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs further comprises a first electrical contact region, wherein the first electrical contact region and the first ACS are coterminous, and wherein the at least one switch NMOSFET of the first plurality of switch NMOSFETs further comprises a second electrical contact region, wherein the second electrical contact region and the second ACS are coterminous.

46. The RF switch of claim 45, wherein the first electrical contact region is positioned proximate to and in electrical contact with the first ACS, and wherein the second electrical contact region is positioned proximate to and in electrical contact with the second ACS.

47. The RF switch of claim 43, wherein the first ACS and second ACS are electrically coupled to the gate.

48. The RF switch of claim 43, wherein the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs comprises an enhancement mode NMOSFET.

49. The RF switch of claim 43, wherein the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs comprises a depletion mode NMOSFET.

50. The RF switch of claim 43, 44 or 46, wherein the RF switch is capable of processing input signals having power levels equal to or less than 35 dBm.

51. The RF switch of claim 43, 44 or 46, wherein the width of the first body is greater than 10 μ

m and the width of the second body is greater than 10 μ

m.

52. The RF switch of claim 43, 44 or 46, wherein the first and second switch transistor groupings and the first shunt transistor grouping are fabricated in a silicon layer having a thickness between about 100 angstroms to about 2,000 angstroms.

53. The RF switch of claim 43, 44 or 46, wherein the first ACS bias voltage applied to the first ACS and the second ACS bias voltage applied to the second ACS are negative with respect to ground and have a magnitude of approximately 2.5V in an off-state (non-conducting state).

54. The RF switch of claim 53, wherein the first ACS bias voltage applied to the first ACS and the second ACS bias voltage applied to the second ACS have a voltage level in an on-state (conducting state) that is different from a voltage level in an off-state (non-conducting state).

55. The RF switch of claim 43, 44 or 46, wherein the first and second switch transistor groupings and the first shunt transistor grouping are fabricated in a silicon layer having a thickness of approximately 100 angstroms to approximately 2,000 angstroms, and wherein the first ACS bias voltage applied to the first ACS and the second ACS bias voltage applied to the second ACS are negative with respect to ground and have a magnitude of approximately 2.5V in an off-state (non-conducting state).

56. The RF switch of claim 43, 44 or 46, wherein the first ACS bias voltage and the second ACS bias voltage have the same magnitude.

57. An RF switch, comprising:

a first RF port;

a second RF port;

a first switch transistor grouping coupled to the first RF port and to the second RF port and comprising a first plurality of switch NMOSFETs arranged in a stacked configuration;

a first shunt transistor grouping coupled to the first RF port and to ground and comprising a first plurality of shunt NMOSFETs arranged in a stacked configuration,

wherein at least one of the first plurality of shunt NMOSFETs comprises a first gate, a first source, a first drain, a first body, a first accumulated charge sink (ACS) coupled to the first body, wherein the first ACS is positioned proximate a first distal end of the first body and is in electrical communication with the first body, and a second accumulated charge sink (ACS) coupled to the first body, wherein the second ACS is positioned proximate a second distal end of the first body and is in electrical communication with the first body,

wherein a first ACS bias voltage is applied to the first ACS and second ACS,

wherein, when the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs is configured to operate in an off-state (non-conducting state), the first ACS bias voltage is substantially negative with respect to ground to substantially prevent accumulated charge from accumulating in the first body of the at least one shunt NMOSFET; and

wherein the first switch transistor grouping and the first shunt transistor grouping are fabricated on a silicon-on-insulator substrate.

58. The RF switch of claim 57, wherein preventing accumulated charge from accumulating in the first body of the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs improves linearity of the at least one shunt NMOSFET.

59. The RF switch of claim 58, further comprising:

a first electrical contact region positioned proximate to and in electrical communication with the first ACS, wherein the first electrical contact region facilitates electrical coupling to the first ACS; and

a second electrical contact region positioned proximate to and in electrical communication with the second ACS, wherein the second electrical contact region facilitates electrical coupling to the second ACS.

60. The RF switch of claim 59, wherein the first ACS and first electrical contact region are coterminous and wherein the second ACS and second electrical contact region are coterminous.

61. The RF switch of claim 59, wherein the first ACS and second ACS are electrically coupled to the gate.

62. The RF switch of claim 59, wherein the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs comprises an enhancement mode NMOSFET.

63. The RF switch of claim 59, wherein the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs comprises a depletion mode NMOSFET.

64. The RF switch of claim 58 or 59, wherein the width of the first body is greater than 10 μ

m.

65. The RF switch of claim 58 or 59, wherein the RF switch is capable of processing input signals having power levels equal to or less than 35 dBm.

66. The RF switch of claim 58 or 59, wherein the first switch transistor grouping and the first shunt transistor grouping are fabricated in a silicon layer having a thickness between about 100 angstroms to about 2,000 angstroms.

67. The RF switch of claim 58 or 59, wherein the first ACS bias voltage applied to the first ACS and the second ACS are negative with respect to ground and have a magnitude of approximately 2.5V in an off-state (non-conducting state).

68. The RF switch of claim 67, wherein the first ACS bias voltage applied to the first ACS and the ACS has a voltage level in an on-state (conducting state) that is different from a voltage level in an off-state (non-conducting state).

69. The RF switch of claim 58 or 59, wherein the first switch transistor grouping and the first shunt transistor grouping are fabricated in a silicon layer having a thickness of approximately 100 angstroms to approximately 2,000 angstroms, and wherein the first negative bias voltage applied to the first ACS and the second ACS are negative with respect to ground and have a magnitude of approximately 2.5V in an off-state (non-conducting state).

70. An RF switch, comprising:

a first RF port;

a second RF port;

a first switch transistor grouping coupled to the first RF port and to the second RF port and comprising a first plurality of switch NMOSFETs arranged in a stacked configuration;

a first shunt transistor grouping coupled to the first RF port and to ground and comprising a first plurality of shunt NMOSFETs arranged in a stacked configuration,

wherein at least one of the first plurality of shunt NMOSFETs comprises a first gate, a first source, a first drain, a first body, a first accumulated charge sink (ACS) coupled to the first body, wherein the first ACS is positioned proximate a first distal end of the first body and is in electrical communication with the first body, and a second accumulated charge sink (ACS) coupled to the first body, wherein the second ACS is positioned proximate a second distal end of the first body and is in electrical communication with the first body,

wherein a first ACS bias voltage is applied to the first ACS and second ACS,

wherein, when the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs is configured to operate in an off-state (non-conducting state), the first ACS bias voltage is substantially more negative than the lesser of a first source bias voltage applied to the first source and a first drain bias voltage applied to the first drain to substantially prevent accumulated charge from accumulating in the first body of the at least one shunt NMOSFET; and

wherein the first switch transistor grouping and the first shunt transistor grouping are fabricated on a silicon-on-insulator substrate.

71. The RF switch of claim 70, wherein preventing accumulated charge from accumulating in the first body of the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs improves linearity of the at least one shunt NMOSFET.

72. The RF switch of claim 71, further comprising:

a first electrical contact region positioned proximate to and in electrical communication with the first ACS, wherein the first electrical contact region facilitates electrical coupling to the first ACS; and

a second electrical contact region positioned proximate to and in electrical communication with the second ACS, wherein the second electrical contact region facilitates electrical coupling to the second ACS.

73. The RF switch of claim 72, wherein the first ACS and first electrical contact region are coterminous and wherein the second ACS and second electrical contact region are coterminous.

74. The RF switch of claim 72, wherein the first ACS and second ACS are electrically coupled to the gate.

75. The RF switch of claim 72, wherein the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs comprises an enhancement mode NMOSFET.

76. The RF switch of claim 72, wherein the at least one shunt NMOSFET of the first plurality of shunt NMOSFETs comprises a depletion mode NMOSFET.

77. The RF switch of claim 71 or 72, wherein the width of the first body is greater than 10 μ

m.

78. The RF switch of claim 71 or 72, wherein the RF switch is capable of processing input signals having power levels equal to or less than 35 dBm.

79. The RF switch of claim 71 or 72, wherein the first switch transistor grouping and the first shunt transistor grouping are fabricated in a silicon layer having a thickness between about 100 angstroms to about 2,000 angstroms.

80. The RF switch of claim 71 or 72, wherein the first ACS bias voltage applied to the first ACS and the second ACS is negative with respect to ground and has a magnitude of approximately 2.5V in an off-state (non-conducting state).

81. The RF switch of claim 80, wherein the first ACS bias voltage applied to the first ACS and the second ACS has a voltage level in an on-state (conducting state) that is different from a voltage level in an off-state (non-conducting state).

82. The RF switch of claim 71 or 72, wherein the first switch transistor grouping and the first shunt transistor grouping are fabricated in a silicon layer having a thickness of approximately 100 angstroms to approximately 2,000 angstroms, and wherein the first negative bias voltage applied to the first ACS and the second ACS is negative with respect to ground and has a magnitude of approximately 2.5V in an off-state (non-conducting state).