GLOBAL BIT LINE PRE-CHARGE CIRCUIT THAT COMPENSATES FOR PROCESS, OPERATING VOLTAGE, AND TEMPERATURE VARIATIONS

• US 20130294136A1
• Filed: 07/03/2013
• Published: 11/07/2013
• Est. Priority Date: 06/10/2011
• Status: Active Grant

• Current Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Original Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Inventors: Siau, Chang Hua, Bateman, Bruce Lynn
• Granted Patent: US 9,117,495 B2
• Time in Patent Office: Days
• US Class Current: 365/66
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/08 for interconnecting magnetic elements, e.g. toroidal cores
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

Claims

1. A method of operating a cross point memory array comprising a plurality of word lines and a plurality of bit lines, wherein the plurality of bit lines comprises a plurality of local bit lines, each electrically connected to a corresponding one of a plurality of global bit lines by respective corresponding one of a plurality of gain stage transistors, the plurality of gain stage transistors having parameters that vary with respect to at least one of process, voltage, and temperature, the method comprising:

precharging a first selected local bit line of the plurality of local bit lines to a first voltage that varies with the transistor parameters of the corresponding gain stage transistor; and

after precharging the first selected local bit line, applying a voltage to a selected word line of the cross point memory array to read a memory cell coupled between the selected local bit line and the selected word line.

2. The method of claim 1, further comprising, coincident with precharging the first selected local bit line, precharging a second selected local bit line of the plurality of local bit lines to a second voltage, different than the first voltage, that varies with the transistor parameters of the gain stage transistor corresponding to the second selected local bit line.

3. The method of claim 1, wherein the first voltage corresponds to a voltage threshold of the corresponding gain stage transistor.

4. The method of claim 1, wherein precharging the first selected local bit line to the first voltage further comprises floating the selected word line.

5. The method of claim 1, wherein precharging the first selected local bit line comprises:

activating a first write transistor of the cross point memory array to short the first local bit line to its corresponding global bit line; and

responsive to said shorting, applying a preset current to the corresponding global bit line to bias the corresponding gain stage transistor to the first voltage.

6. The method of claim 5, wherein a value of the preset current is in correspondence with a value of a read current associated with the memory cell.

7. The method of claim 5, further comprising holding inactive a second write transistor of the cross point memory array while the first write transistor is activated, wherein the second write transistor is coupled to the same global bit line as the first write transistor and corresponds to a non-selected local bit line of the plurality of local bit lines.

8. The method of claim 5, further comprising:

after applying the preset current to the corresponding global bit line, deactivating the first write transistor to trap a charge on the first selected local bit line.

9. The method of claim 8, further comprising:

after deactivating the first write transistor, precharging the corresponding global bit line with a voltage that coincides with a read voltage associated with the memory cell.

10. A memory device, comprising:

a plurality of word lines and a plurality of bit lines, wherein the plurality of bit lines comprises a plurality of local bit lines, each electrically connected to a corresponding one of a plurality of global bit lines by respective corresponding one of a plurality of gain stage transistors, the plurality of gain stage transistors having transistor parameters that vary with at least one of process, voltage, and temperature;

a plurality of two-terminal memory elements, each two-terminal memory element coupled between a respective word line of the plurality of word lines and a respective bit line of the plurality of bit lines;

a controller coupled to the plurality of gain stage transistors, the controller configured to;

precharge a first selected local bit line of the plurality of bit lines to a first voltage that varies with the transistor parameters of the corresponding gain stage transistor; and

after precharging the first selected local bit line, applying a voltage to a selected word line of the cross point memory array to read the memory element coupled between the first selected local bit line and the selected word line.

11. The memory device of claim 10, wherein the controller is further configured to, coincident with precharging the first selected local bit line, precharge a second selected local bit line of the plurality of local bit lines to a second voltage, different than the first voltage, that varies with the transistor parameters of the gain stage transistor corresponding to the second selected local bit line.

12. The memory device of claim 11, wherein the first voltage corresponds to a voltage threshold of the corresponding gain stage transistor.

13. The memory device of claim 10, wherein precharging the first selected local bit line to the first voltage further comprises floating the selected word line.

14. The memory device of claim 10, wherein precharging the first selected local bit line comprises:

activate a first write transistor of the cross point memory array to short the first local bit line to its corresponding global bit line; and

responsive to said shorting, apply a preset current to the corresponding global bit line to bias the corresponding gain stage transistor to the first voltage.

15. The memory device of claim 14, wherein a value of the preset current is in correspondence with a value of a read current associated with the memory cell.

16. The memory device of claim 15, wherein the controller is further configured to hold inactive a second write transistor of the cross point memory array while the first write transistor is activated, wherein the second write transistor is coupled to the same global bit line as the first write transistor and corresponds to a non-selected local bit line of the plurality of local bit lines.

17. The memory device of claim 15, wherein the controller is further configured to:

after applying the preset current to the corresponding global bit line, deactivate the first write transistor to trap a charge on the first selected local bit line.

18. The memory device of claim 17, wherein the controller is further configured to:

after deactivating the first write transistor, precharge the corresponding global bit line with a voltage that coincides with a read voltage associated with the memory cell.