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LOW-VOLTAGE FAST-WRITE NVSRAM CELL

  • US 20130294161A1
  • Filed: 05/06/2013
  • Published: 11/07/2013
  • Est. Priority Date: 05/07/2012
  • Status: Abandoned Application
First Claim
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1. A 16T NVSRAM memory cell circuit with low-voltage fast-write scheme, the 16T NVSRAM memory cell comprising:

  • a SRAM cell comprising a first access transistor and a second access transistor sharing a first word line and respectively coupling between a first bit line and a first data node and between a second bit line and a second data node, the first data node and the second data node respectively being coupled to two cross-coupled invertors made by four LV CMOS transistors;

    a Flash cell comprising a first cell string and a second cell string sharing a common P-sub, the first/second cell string including a first/second top Select transistor, a first/second Flash transistor, and a first/second bottom Select transistor connected in series, the first and the second top Select transistors being gated commonly by a first select-gate control line and respectively associated with a first drain terminal and a second drain terminal, the first and the second bottom Select transistors being gated commonly by a second select-gate control line and respectively associated with a first source terminal and a second source terminal, the first and the second Flash transistors being gated commonly by a second word line, the first source terminal and the second source terminal being connected together to a flash source line; and

    a Bridge circuit including a first, second, third, and fourth LV NMOS transistor for connecting the first data node and the second data node of the SRAM cell respectively through two cross routes to the first drain terminal and the second drain terminal of the Flash cell, wherein the first and the third LV NMOS transistors are commonly gated by a FSwrite control line and the second and the fourth LV NMOS transistors are commonly gated by a SFwrite control line;

    wherein the first and the second LV NMOS transistors have a first common drain node connected to the first data node of the SRAM cell;

    the second and the third LV NMOS transistors have a first common source node connected to the first drain terminal of the Flash cell;

    wherein the third and the fourth LV NMOS transistors have a second common drain node connected to the second data node of the SRAM cell;

    the first and the fourth LV NMOS transistors have a second common source node connected to the second drain terminal of the Flash cell;

    wherein only one of the FSwrite control line and the SFwrite control line is turned on at a time by coupling to a power supply voltage as low as 1.2 V Vdd for providing a direct route of writing data from the SRAM cell to the Flash cell via a FN tunneling effect by setting only one HV of +12V or lower the second word line and providing an alternate route of loading data from the Flash cell to the SRAM cell by conducting current from the first or second data node to a grounded flash source line so that a reversed polarity of each data from the Flash cell can be reversely loaded into the SRAM cell operating at the power supply voltage as low as 1.2 V Vdd.

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