LOW-VOLTAGE FAST-WRITE NVSRAM CELL

• US 20130294161A1
• Filed: 05/06/2013
• Published: 11/07/2013
• Est. Priority Date: 05/07/2012
• Status: Abandoned Application

• Current Assignee: Aplus Flash Technology, Inc.
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Lee, Peter Wung, Tsao, Hsing-Ya
• Application Number:
  US13/888,134
• Publication Number:
  US 20130294161A1
• Time in Patent Office: Days
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence

Abstract

This invention discloses several embodiments of a low-voltage fast-write NVSRAM cells, made of either of a 2-poly floating-gate type flash cell or a 1-poly charge-trapping SONOS or MONOS flash cell with improvement by adding a Bridge circuit. This Bridge circuit is preferably inserted between each LV 6T SRAM cell and each HV Flash cell that comprises one paired complementary Flash strings. The Flash strings can be made of either 2T or 3T Flash strings. The tradeoff of using either a 2T or a 3T Flash string is subject to the gate area penalty and required design specs. One improvement for adding the Bridge circuit into the NVSRAM cell is to ensure the data writing between Flash cell and SRAM cell with the same polarity and to allow the operation down to low 1.2V Vdd.

Claims

1. A 16T NVSRAM memory cell circuit with low-voltage fast-write scheme, the 16T NVSRAM memory cell comprising:

a SRAM cell comprising a first access transistor and a second access transistor sharing a first word line and respectively coupling between a first bit line and a first data node and between a second bit line and a second data node, the first data node and the second data node respectively being coupled to two cross-coupled invertors made by four LV CMOS transistors;

a Flash cell comprising a first cell string and a second cell string sharing a common P-sub, the first/second cell string including a first/second top Select transistor, a first/second Flash transistor, and a first/second bottom Select transistor connected in series, the first and the second top Select transistors being gated commonly by a first select-gate control line and respectively associated with a first drain terminal and a second drain terminal, the first and the second bottom Select transistors being gated commonly by a second select-gate control line and respectively associated with a first source terminal and a second source terminal, the first and the second Flash transistors being gated commonly by a second word line, the first source terminal and the second source terminal being connected together to a flash source line; and

a Bridge circuit including a first, second, third, and fourth LV NMOS transistor for connecting the first data node and the second data node of the SRAM cell respectively through two cross routes to the first drain terminal and the second drain terminal of the Flash cell, wherein the first and the third LV NMOS transistors are commonly gated by a FSwrite control line and the second and the fourth LV NMOS transistors are commonly gated by a SFwrite control line;

wherein the first and the second LV NMOS transistors have a first common drain node connected to the first data node of the SRAM cell;

the second and the third LV NMOS transistors have a first common source node connected to the first drain terminal of the Flash cell;

wherein the third and the fourth LV NMOS transistors have a second common drain node connected to the second data node of the SRAM cell;

the first and the fourth LV NMOS transistors have a second common source node connected to the second drain terminal of the Flash cell;

wherein only one of the FSwrite control line and the SFwrite control line is turned on at a time by coupling to a power supply voltage as low as 1.2 V Vdd for providing a direct route of writing data from the SRAM cell to the Flash cell via a FN tunneling effect by setting only one HV of +12V or lower the second word line and providing an alternate route of loading data from the Flash cell to the SRAM cell by conducting current from the first or second data node to a grounded flash source line so that a reversed polarity of each data from the Flash cell can be reversely loaded into the SRAM cell operating at the power supply voltage as low as 1.2 V Vdd.

2. The 16T NVSRAM memory cell of claim 1 wherein each of the first and second top/bottom Select transistors is an 1-poly HV NMOS transistor formed by shorting a Poly2 control gate to a Poly1 floating gate of a 2-poly HV NMOS floating-gate transistor.

3. The 16T NVSRAM memory cell of claim 1 wherein each of the first and second Flash transistors is a 2-poly floating-gate type NMOS transistor.

4. The 16T NVSRAM memory cell of claim 1 wherein each of the first and second Flash transistors is an1-poly charge-trapping type SONOS or MONOS transistor.

5. The 16T NVSRAM memory cell of claim 3 wherein the Flash cell is subjected to an erase operation by setting the second word line to a negative voltage no greater than −

12V to achieve a FN-tunneling effect on each 2-poly floating-gate type NMOS transistor with respect to 0 V applied to the first select-gate control line, the flash source line, and the common P-sub and the Vdd level applied to the second select-gate control line.

6. The 16T NVSRAM memory cell of claim 4 wherein the Flash cell is subjected to an erase operation by setting the second word line to a negative voltage no greater than −

7V to achieve a FN-tunneling effect on each 1-poly charge-trapping type SONOS or MONOS transistor with respect to 0 V applied to the first select-gate control line, the flash source line, and the common P-sub and the Vdd level applied to the second select-gate control line.

7. The 16T NVSRAM memory cell of claim 1 wherein the Flash cell is erased via FN-tunneling effect to bring a threshold voltage level of each of the first Flash transistor and the second Flash transistor to a V_t0 level of −

2V or smaller within 10 ms for cell density greater than 200 Mb.

8. The 16T NVSRAM memory cell of claim 1 wherein the Flash cell is erased independent to the SRAM cell wherein each of the first data node and the second data node is isolated from the Flash cell by grounding both the FSwrite control line and the SFwrite control line.

9. The 16T NVSRAM memory cell of claim 1 wherein the Flash cell is subjected to a Writing operation from the SRAM cell having the first data node at Vss=0V level and the second data node at the Vdd level to cause the first Flash transistor being subjected to a program operation to increase its threshold voltage level from a V_t0 level of no greater than −

2V to a V_t1 level of greater than +2V and the second Flash transistor being subjected to a program-inhibit operation to retain its threshold voltage level at the V_t0 level.

10. The 16T NVSRAM memory cell of claim 9 wherein the Writing operation from the SRAM cell is associated with following control bias conditions including setting the Vss to the first word line, setting +12V or lower to the second word line connect a gate of a 2-poly floating-gate NMOS transistor of the first Flash transistor, setting the Vdd to the SFwrite control line to open a direct route from the first data node through the second LV NMOS transistor to the first Flash transistor and from the second data node through the fourth LV NMOS transistor to the second Flash transistor, setting the Vss to the FSwrite control line, setting the Vdd to the first select-gate control line, setting the Vss to the second select-gate control line, and keeping the flash source line and the common P-sub to the Vss.

11. The 16T NVSRAM memory cell of claim 9 wherein the first Flash transistor is programmed within 10 ms for cell density greater than 200 Mb.

12. The 16T NVSRAM memory cell of claim 9 wherein the second Flash transistor subjecting to the program-inhibit operation by coupling a channel voltage of greater than 5 V for the corresponding 2-poly floating-gate type NMOS transistor to not induce a FN tunneling effect when the second word line is set to +12V and its drain node being coupled to the Vdd level from the second data node as the SFwrite control line and the first select-gate control line are set to the Vdd level.

13. The 16T NVSRAM memory cell of claim 1 wherein the SRAM cell is subjected to a read operation by setting the first word line to the Vdd level, the read operation being isolated from the Flash cell by setting the SFwrite control line, the FSwrite control line, and the first select-gate control line to the Vss level.

14. The 16T NVSRAM memory cell of claim 1 wherein the SRAM cell is subjected to a Writing operation from the Flash cell having the first Flash transistor at a threshold voltage level of V_t1 of greater than +2V and the second Flash transistor at a threshold voltage level of V_t0 of smaller than −

2V to cause the first data node to be reset to the Vss level and the second data node correspondingly to be reset to the Vdd level.

15. The 16T NVSRAM memory cell of claim 14 wherein the Writing operation from the Flash cell is a associated with following control bias conditions including setting the Vss to the first word line, setting the Vdd to the second word line, setting the Vss to the SFwrite control line, setting the Vdd to the FSwrite control line to open a reverse route from the second Flash transistor through the first LV NMOS transistor to the first data node and from the first Flash transistor through the third LV NMOS transistor to the second data node, setting the Vdd to the first select-gate control line and the second select-gate control line, and keeping the flash source line and the common P-sub to the Vss.

16. The 16T NVSRAM memory cell of claim 14 wherein the second Flash transistor at the V_t0 of smaller than −

2V causes a current flow from the first data node at the Vdd level through the first LV NMOS transistor, the second top Select transistor, the second Flash transistor, and the second bottom Select transistor, all gated by the Vdd level, to the flash source line that is grounded at the Vss to reset the first data node to the Vss level.

17. The 16T NVSRAM memory cell of claim 14 wherein the first Flash transistor at the V_t1 of greater than +2V blocks a current flow from the second data node through the third LV NMOS transistor to the flash source line.

18. A 14T NVSRAM memory cell circuit with low-voltage fast-write scheme, the 14T NVSRAM memory cell comprising:

a SRAM cell comprising a first access transistor and a second access transistor sharing a first word line and respectively coupling between a first bit line and a first data node and between a second bit line and a second data node, the first data node and the second data node respectively being coupled to two cross-coupled invertors made by four LV CMOS transistors;

a Flash cell comprising a first cell string and a second cell string sharing a common P-sub, the first/second cell string including at least a first/second Flash transistor connected in series to a first/second Select transistor, the first and the second Select transistors being gated commonly by a select-gate control line and respectively associated with a first source terminal and a second source terminal, the first and the second Flash transistors being gated commonly by a second word line, the first source terminal and the second source terminal being connected together to a flash source line; and

a Bridge circuit including a first, second, third, and fourth HV NMOS transistor for connecting the first data node and the second data node of the SRAM cell respectively through two cross routes to the first drain terminal and the second drain terminal of the Flash cell, wherein the first and the third HV NMOS transistors are commonly gated by a FSwrite control line and the second and the fourth HV NMOS transistors are commonly gated by a SFwrite control line;

wherein the first and the second HV NMOS transistors have a first common drain node connected to the first data node of the SRAM cell;

the second and the third HV NMOS transistors have a first common source node connected to the first drain terminal of the Flash cell;

wherein the third and the fourth HV NMOS transistors have a second common drain node connected to the second data node of the SRAM cell;

the first and the fourth HV NMOS transistors have a second common source node connected to the second drain terminal of the Flash cell;

wherein only one of the FSwrite control line and the SFwrite control line is turned on at a time by coupling to a power supply voltage as low as 1.2 V Vdd for providing a direct route of writing data from the SRAM cell to the Flash cell via a FN tunneling effect by setting only one HV of +12V or lower the second word line and providing an alternate route of loading data from the Flash cell to the SRAM cell by conducting current from the first or second data node to a grounded flash source line so that a reversed polarity of each data from the Flash cell can be reversely loaded into the SRAM cell operating at the power supply voltage as low as 1.2V Vdd.

19. The 14T NVSRAM memory cell of claim 18 wherein each of the first and second Select transistors is an 1-poly HV NMOS transistor formed by shorting a Poly2 control gate to a Poly1 floating gate of a 2-poly floating-gate NMOS transistor.

20. The 14T NVSRAM memory cell of claim 18 wherein each of the first and second Flash transistors is a 2-poly floating-gate type NMOS transistor configured to have an increased gate area for achieving increased coupling charges.

21. The 14T NVSRAM memory cell of claim 18 wherein each of the first and second Flash transistors is an1-poly charge-trapping type SONOS or MONOS transistor configured to have an increased gate area for achieving increased coupling charges.

22. The 14T NVSRAM memory cell of claim 20 wherein the Flash cell is subjected to an erase operation by setting the second word line to a negative voltage no greater than −

12V to achieve a FN-tunneling effect on each 2-poly floating-gate type NMOS transistor with respect to 0 V applied to the flash source line and the common P-sub and the Vdd level applied to the select-gate control line.

23. The 14T NVSRAM memory cell of claim 21 wherein the Flash cell is subjected to an erase operation by setting the second word line to a negative voltage no greater than −

7V to achieve a FN-tunneling effect on each 1-poly charge-trapping type SONOS or MONOS transistor with respect to 0 V applied to the flash source line and the common P-sub and the Vdd level applied to the select-gate control line.

24. The 14T NVSRAM memory cell of claim 18 wherein the Flash cell is erased via FN-tunneling effect to bring a threshold voltage level of each of the first Flash transistor and the second Flash transistor to a V_t0 level of −

2V or smaller within 10 ms for NVSRAM cell density greater than 200 Mb.

25. The 14T NVSRAM memory cell of claim 18 wherein the Flash cell is erased independent to the SRAM cell wherein each of the first data node and the second data node is isolated from the Flash cell by grounding both the FSwrite control line and the SFwrite control line.

26. The 14T NVSRAM memory cell of claim 18 wherein the Flash cell is subjected to a Writing operation from the SRAM cell having the first data node at the Vdd level and the second data node at Vss=0V level to cause the second Flash transistor being subjected to a program operation to increase its threshold voltage level from a V_t0 level of no greater than −

2V to a V_t1 level of greater than +2V and the first Flash transistor being subjected to a program-inhibit operation to retain its threshold voltage level at the V_t0 level.

27. The 14T NVSRAM memory cell of claim 26 wherein the Writing operation from the SRAM cell is associated with following control bias conditions including setting the Vss to the first word line, setting +12V or lower to the second word line connect a gate of a 2-poly floating-gate NMOS transistor of the first Flash transistor, setting the Vdd to the SFwrite control line to open a direct route from the first data node through the second HV NMOS transistor to the first Flash transistor and from the second data node through the fourth HV NMOS transistor to the second Flash transistor, setting the Vss to the FSwrite control line, setting the Vss to the select-gate control line, and keeping the flash source line and the common P-sub to the Vss.

28. The 14T NVSRAM memory cell of claim 26 wherein the first Flash transistor is programmed within 10 ms for NVSRAM cell density greater than 200 Mb.

29. The 14T NVSRAM memory cell of claim 26 wherein the first Flash transistor subjecting to the program-inhibit operation by coupling a channel voltage of greater than 5 V for the corresponding 2-poly floating-gate type NMOS transistor to not induce a FN tunneling effect when the second word line is set to +12V and its drain node being coupled to the Vdd level from the first data node as the SFwrite control line is set to the Vdd level.

30. The 14T NVSRAM memory cell of claim 18 wherein the SRAM cell is subjected to a read operation by setting the first word line to the Vdd level, the read operation being isolated from the Flash cell by at least setting the SFwrite control line and the FSwrite control line to the Vss level.

31. The 14T NVSRAM memory cell of claim 18 wherein the SRAM cell is subjected to a Writing operation from the Flash cell having the second Flash transistor at a threshold voltage level of V_t1 of greater than +2V and the first Flash transistor at a threshold voltage level of V_t0 of smaller than −

2V to cause the second data node to be reset to the Vss level and the first data node correspondingly to be reset to the Vdd level.

32. The 14T NVSRAM memory cell of claim 31 wherein the Writing operation from the Flash cell is a associated with following control bias conditions including setting the Vss to the first word line, setting the Vdd to the second word line, setting the Vss to the SFwrite control line, setting the Vdd to the FSwrite control line to open a reverse route from the second Flash transistor through the first HV NMOS transistor to the first data node and from the first Flash transistor through the third HV NMOS transistor to the second data node, setting the Vdd to the select-gate control line, and keeping the flash source line and the common P-sub to the Vss.

33. The 14T NVSRAM memory cell of claim 31 wherein the first Flash transistor at the V_t0 of smaller than −

2V causes a current flow from the second data node at the Vdd level through the third HV NMOS transistor, the first Flash transistor, and the first Select transistor, all gated by the Vdd level, to the flash source line that is grounded at the Vss to reset the first data node to the Vss level.

34. The 14T NVSRAM memory cell of claim 18 wherein the Flash cell is subjected to a Writing operation from the SRAM cell having the first data node at the Vdd level and the second data node at Vss=0V level to cause the second Flash transistor being subjected to a program operation to increase its threshold voltage level from a V_t0 level of no greater than −

2V to a V_t1 level of greater than +2V and the first Flash transistor being subjected to a program-inhibit operation to retain its threshold voltage level at the V_t0 level.