FLASH-BASED MEMORY SYSTEM WITH ROBUST BACKUP AND RESTART FEATURES AND REMOVABLE MODULES

• US 20130294163A1
• Filed: 07/02/2013
• Published: 11/07/2013
• Est. Priority Date: 08/11/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: FROST, Holloway H., SHELTON, Lance W., DAVIS, Don D., GLOVER, Adrian P.
• Granted Patent: US 9,361,984 B2
• Time in Patent Office: Days
• US Class Current: 365/185.11
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 11/07 Responding to the occurrence of a fault, e.g. fault tolerance
• CPC Class Codes: G06F 11/1451 by selection of backup contents
• CPC Class Codes: G06F 11/1469 Backup restoration techniques
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2201/805 Real-time
• CPC Class Codes: G06F 2201/85 Active fault masking without idle spares active fault masking without idle spare hardware where processing functionality is redundant G06F11/2035
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory

Abstract

A Flash-based memory system comprises a plurality of Flash memory devices, a Flash controller communicating independently with each Flash memory device to perform memory operations, a power circuit providing power the Flash memory devices, and a CPU configured to perform a controlled powering down procedure upon detecting a power failure. In some embodiments, the Flash-based memory system includes a backup power source having a charge storage device and charging circuitry, the CPU configured to perform one or more test procedures on the charge storage device to provide an indication of a charge storage capacity of the charge storage device. A plurality of Flash-based memory systems may be mounted on a Flash-based memory card, and multiple such Flash-based memory cards may be combined into a Flash-based memory module. A number of Flash-based memory modules may then be removably mounted in a rack-mountable housing to form unitary Flash-based memory unit.

Claims

1. A Flash-based memory system having a backup power source, comprising:

a printed circuit board (PCB);

a plurality of Flash memory devices mounted to the PCB, each Flash memory device having a physical memory space that is divided into blocks, each block being further divided into pages, each page representing an individually addressable memory location on which memory operations are performed, multiple memory locations being erased at the same time in one-block groupings;

a Flash controller mounted to the PCB and communicating independently with each Flash memory device to perform the memory operations;

a power circuit mounted to the PCB and providing power to the Flash memory devices, the power being provided from a primary power source during normal operation of the Flash-based memory system and from a backup power source when the primary power source falls below a predefined level, the backup power source including a charge storage device and charging circuitry configured to charge the charge storage device; and

a central processing unit (CPU) mounted to the PCB and coupled to the power circuit and the Flash controller, the CPU configured to perform one or more test procedures on the charge storage device and provide an indication of a charge storage capacity of the charge storage device, the one or more test procedures comprising;

disabling the charging circuitry from charging the charge storage device;

obtaining a first voltage measurement from the charge storage device;

applying a predefined load to the charge storage device;

obtaining a second voltage measurement from the charge storage device;

waiting a predefined amount of time; and

obtaining a third voltage measurement from the charge storage device;

wherein the CPU provides an indication of the charge storage capacity of the charge storage device by providing at least one of a capacitance C of the charge storage device and an equivalent series resistance (ESR) of the charge storage device based on one or more of the first, second, and third voltage measurements.

2. The Flash-based memory system according to claim 1, wherein the one or more test procedures further comprises obtaining an initial voltage measurement from the storage device prior to disabling the charging circuitry and continuing with the one or more test procedures only if the initial voltage measurement exceeds a first predefined threshold.

3. The Flash-based memory system according to claim 1, wherein the one or more test procedures further comprises determining whether the first voltage measurement exceeds a second predefined threshold and continuing with the one or more test procedures only if the first voltage measurement exceeds the second predefined threshold.

4. The Flash-based memory system according to claim 1, wherein the one or more test procedures further comprises determining whether the second voltage measurement exceeds a third predefined threshold and continuing with the one or more test procedures only if the second voltage measurement exceeds the third predefined threshold.

5. The Flash-based memory system according to claim 1, wherein the CPU is configured to provide the capacitance C and the ESR of the charge storage device using the following equations in which the first, second, and third voltage measurements are represented as V1, V2, and V3, respectively, the predefined amount of time is represented as t1, and the predefined load is represented as R:

6. The Flash-based memory system according to claim 5, wherein the CPU is further configured to perform the one or more test procedures on the charge storage device a predefined number of iterations, measure V1, V2, and V3, respectively, for each iteration, determine an average measurement for V1, V2, and V3, respectively, over the predefined number of iterations, and calculate a capacitance C and an ESR for the charge storage device.

7. The Flash-based memory system according to claim 1, wherein the CPU is further configured to perform the one or more test procedures on the charge storage device a predefined number of iterations, calculate the capacitance C and the ESR of the charge storage device for each iteration, and determine an average capacitance C and an average ESR for the charge storage device over the predefined number of iterations.

8. The Flash-based memory system according to claim 1, wherein the power circuit includes power selection circuitry configured to select between a primary power and a backup power, the power selection circuitry being implemented using one of the following arrangements:

i) a first switching element receiving the primary power as an input and a second switching element receiving the backup power as an input, the first and second switching elements having outputs that are connected together; and

ii) a first switching device controller receiving the primary power as an input and controlling a first switching device and a second switching device controller receiving the backup power as an input and controlling a second switching device, the first and second switching devices having outputs that are connected together.

9. A method of testing a Flash-based memory system having a backup power source, comprising:

providing power to the Flash-based memory system, the power being provided from a primary power source during normal operation of the Flash-based memory system and from a backup power source when the primary power source falls below a predefined level, the backup power source including a charge storage device and charging circuitry configured to charge the charge storage device;

automatically performing one or more test procedures on the charge storage device and providing an indication of a charge storage capacity of the charge storage device, the one or more test procedures comprising;

disabling the charging circuitry from charging the charge storage device;

obtaining a first voltage measurement from the charge storage device;

applying a predefined load to the charge storage device;

obtaining a second voltage measurement from the charge storage device;

waiting a predefined amount of time; and

obtaining a third voltage measurement from the charge storage device;

wherein providing an indication of the charge storage capacity of the charge storage device comprises providing at least one of a capacitance C of the charge storage device and an equivalent series resistance (ESR) of the charge storage device based on one or more of the first, second, and third voltage measurements.

10. The method according to claim 9, wherein the one or more test procedures further comprises obtaining an initial voltage measurement from the storage device prior to disabling the charging circuitry and continuing with the one or more test procedures only if the initial voltage measurement exceeds a first predefined threshold.

11. The method according to claim 9, wherein the one or more test procedures further comprises determining whether the first voltage measurement exceeds a second predefined threshold and continuing with the one or more test procedures only if the first voltage measurement exceeds the second predefined threshold.

12. The method according to claim 9, wherein the one or more test procedures further comprises determining whether the second voltage measurement exceeds a third predefined threshold and continuing with the one or more test procedures only if the second voltage measurement exceeds the third predefined threshold.

13. The method according to claim 9, wherein the capacitance C and the ESR of the charge storage device are provided using the following equations in which the first, second, and third voltage measurements are represented as V1, V2, and V3, respectively, the predefined amount of time is represented as t1, and the predefined load is represented as R:

14. The method according to claim 13, wherein the one or more test procedures are performed on the charge storage device a predefined number of iterations, V1, V2, and V3 are measured, respectively, for each iteration, an average measurement for V1, V2, and V3 is determined, respectively, over the predefined number of iterations, and a capacitance C and an ESR are calculated for the charge storage device.

15. The method according to claim 9, wherein the one or more test procedures are performed on the charge storage device a predefined number of iterations, the capacitance C and the ESR of the charge storage device are calculated for each iteration, and an average capacitance C and an average ESR are determined for the charge storage device over the predefined number of iterations.

16. The method according to claim 9, further comprising automatically selecting between a primary power and a backup power, the automatically selecting being implemented using one of the following arrangements:

i) a first switching element receiving the primary power as an input and a second switching element receiving the backup power as an input, the first and second switching elements having outputs that are connected together; and

ii) a first switching device controller receiving the primary power as an input and controlling a first switching device and a second switching device controller receiving the backup power as an input and controlling a second switching device, the first and second switching devices having outputs that are connected together.

17. A Flash-based memory system having a backup power source, comprising:

a plurality of Flash memory devices;

a Flash controller communicating independently with each Flash memory device;

a backup power source providing power to the Flash memory devices when a primary power source falls below a predefined level, the backup power source including a charge storage device; and

a central processing unit (CPU) coupled to the backup power source, the CPU configured to perform one or more predefined test procedures on the charge storage device and provide an indication of a charge storage capacity of the charge storage device, the CPU providing the indication of the charge storage capacity of the charge storage device by providing at least one of a capacitance C of the charge storage device and an equivalent series resistance (ESR) of the charge storage device.

18. The Flash-based memory system according to claim 17, wherein the CPU is configured to provide the capacitance C and the ESR of the charge storage device using the following equations in which V1, V2, and V3 represent first, second, and third voltage measurements from the charge storage device, respectively, R represents a predefined load, and t1 represents a predefined amount of time:

19. The Flash-based memory system according to claim 18, wherein the CPU is further configured to perform the one or more predefined test procedures on the charge storage device a predefined number of iterations, measure V1, V2, and V3, respectively, for each iteration, determine an average measurement for V1, V2, and V3, respectively, over the predefined number of iterations, and calculate a capacitance C and an ESR for the charge storage device.

20. The Flash-based memory system according to claim 17, wherein the CPU is further configured to perform the one or more predefined test procedures on the charge storage device a predefined number of iterations, calculate the capacitance C and the ESR of the charge storage device for each iteration, and determine an average capacitance C and an average ESR for the charge storage device over the predefined number of iterations.