Programmable Semiconductor Interposer for Electronic Package and Method of Forming

• US 20130295727A1
• Filed: 07/01/2013
• Published: 11/07/2013
• Est. Priority Date: 05/29/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Chao-Shun, Chao, Clinton, Peng, Mark Shane
• Granted Patent: US 8,945,998 B2
• Time in Patent Office: Days
• US Class Current: 438/130
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5382 Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/157 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/19011 : including integrated passive components

Abstract

Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in the interposer. A user can program the interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of the interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in the standard interposer to an integrated circuit die encapsulated in the electronic package. Methods of forming the programmable semiconductor interposer and the electronic package are also illustrated.

Claims

1. A method of forming a semiconductor interposer, the method comprising:

forming an array of semiconductor devices having a plurality of electrical parameters in an insulating material on a first surface of a substrate, each semiconductor device of the array of semiconductor devices having a vertical interconnect extending to a first surface of the insulating material;

forming one or more first contact pads on a second surface of the substrate;

forming one or more second contact pads over the insulating material, at least one of the second contact pads being coupled to at least one of the first contact pads; and

obtaining a desired electrical parameter for an integrated circuit device attached to the interposer comprising;

selectively connecting the vertical interconnect of at least one of the array of semiconductor devices to at least one of the second contact pads; and

selectively connecting the vertical interconnect of at least one of the array of semiconductor devices to the vertical interconnect of at least one other of the array of semiconductor devices.

2. The method of claim 1, wherein obtaining the desired electrical parameter for an integrated circuit device attached to the interposer comprises serially connecting at least two of the array of semiconductor devices.

3. The method of claim 1, wherein obtaining the desired electrical parameter for an integrated circuit device attached to the interposer comprises a parallel connection between at least two of the array of semiconductor devices.

4. The method of claim 1, wherein the array of semiconductor devices comprises semiconductor devices being arranged in at least two layers with at least one of the semiconductor devices overlying at least one other of the semiconductor devices.

5. The method of claim 1, wherein obtaining the desired electrical parameter for an integrated circuit device attached to the interposer further comprises:

forming an interconnect matrix having at least two conductive layers in another insulating material;

forming a plurality of one-time programmable fuses or antifuses, each of the plurality of fuses or antifuses being at each intersection of the at least two conductive layers; and

applying a programming voltage to at least two of the plurality of the one-time programmable fuses or antifuses to selectively couple portions of the at least two conductive layers.

6. The method of claim 1, wherein obtaining the desired electrical parameter for an integrated circuit device attached to the interposer further comprises:

forming routing tracks between the array of semiconductor devices;

forming routing switches adjacent the array of semiconductor devices, each of the routing tracks terminating at a routing switch; and

programming the routing switches to selectively connect at least one of the array of semiconductor devices to a routing track.

7. The method of claim 1, wherein the array of semiconductor devices comprises a resistor, a capacitor, an inductor, a transmission line, a fuse, an antifuse, or a microelectromechanical systems device.

8. The method of claim 1 further comprising forming one or more conductive paths through the interposer, the one or more conductive paths coupling at least one of the first contact pads to at least one of the second contact pads.

9. A method of forming a semiconductor interposer, the method comprising:

forming an array of semiconductor devices having a plurality of electrical parameters in an insulating material on a first surface of a substrate, each semiconductor device of the array of semiconductor devices having a vertical interconnect extending to a first surface of the insulating material;

forming one or more first contact pads on a second surface of the substrate;

forming a device selection unit on the insulating material; and

forming one or more second contact pads over the device selection unit, wherein the device selection unit is capable of;

selectively connecting the vertical interconnect of at least one of the array of semiconductor devices to at least one of the second contact pads; and

selectively connecting the vertical interconnect of at least one of the array of semiconductor devices to the vertical interconnect of at least one other of the array of semiconductor devices.

10. The method of claim 9 further comprising forming one or more conductive paths passing through the substrate and connecting at least one of the first contact pads to at least one of the second contact pads.

11. The method of claim 9, wherein forming the device selection unit comprises forming one or more custom conductive layers on the insulating material.

12. The method of claim 9, wherein forming the device selection unit comprises:

forming an interconnect matrix having at least two conductive layers in another insulating material;

forming a plurality of one-time programmable fuses or antifuses, each of the plurality of fuses or antifuses being at each intersection of the at least two conductive layers; and

applying a programming voltage to at least two of the plurality of the one-time programmable fuses or antifuses to selectively couple portions of the at least two conductive layers.

13. The method of claim 9, wherein all of the semiconductor devices in the array of semiconductor devices are a same type of device.

14. The method of claim 9 further comprising forming one or more active devices in the first surface of the substrate, at least one of the one or more active devices being coupled to at least one of the second contact pads.

15. The method of claim 9, wherein the device selection unit selectively connects at least two of the array of semiconductor devices to form a combined device, the combined device having a desired electrical parameter.

16. A method of forming an electronic package, the method comprising:

forming a programmable semiconductor interposer comprising;

forming an array of semiconductor devices having a plurality of electrical parameters in an insulating material on a substrate; and

forming a device selection unit on the insulating material;

forming a plurality of first contact pads on a first surface of the programmable semiconductor interposer;

forming a plurality of second contact pads on a second surface of the programmable semiconductor interposer, the second surface being opposite the first surface;

programming the device selection unit, the programming comprising;

connecting at least two of the array of semiconductor devices to form a custom device; and

connecting at least one of the array of semiconductor devices to at least one of the plurality of first contact pads; and

bonding an integrated circuit die to the first contact pads, the custom device having a desired electrical parameter for the integrated circuit die.

17. The method of claim 16, wherein forming the programmable semiconductor interposer further comprises:

selecting a semiconductor interposer design from an interposer design database; and

designing the device selection unit based on the selected semiconductor interposer design.

18. The method of claim 16, wherein each of the array of semiconductor devices have an interconnect extending to the device selection unit, each of the interconnects being perpendicular to a top surface of the insulating material.

19. The method of the claim 16, wherein connecting the at least two of the array of semiconductor devices to form a custom device comprises serially connecting the at least two of the array of semiconductor devices.

20. The method of the claim 16, wherein programming the device selection unit further comprises:

forming routing tracks between the array of semiconductor devices;

forming routing switches adjacent the array of semiconductor devices, each of the routing tracks terminating at a routing switch; and

programming the routing switches to selectively connect at least one of the array of semiconductor devices to a routing track, the routing switches capable of being reprogrammed to selectively connect at least one other of the array of semiconductor devices to the routing track.